參數(shù)資料
型號(hào)： ML60851D
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： USB Device Controller
中文描述： USB設(shè)備控制器
文件頁數(shù)： 68/82頁
文件大?。?/td> 705K
代理商： ML60851D
FEDL60851D-01
1
Semiconductor
ML60851D
68/82
(4) Receive packet ready interrupts (EP1, EP2)
These interrupts are generated when the respective EP has received an appropriate data packet from the USB
bus and the local MCU can read that data.
Operation
Source of operation
ML60851D
Description (conditions, responses, etc.)
The receive packet ready bit of the corresponding EP
status register (EPnSTAT) is asserted during data
reception when the EOP of the data packet has been
received and the data has been stored without error in the
corresponding FIFO. The end of a packet is recognized
when an EOP has arrived in the cases of both full packets
and short packets.
An interrupt is generated at this time, if the corresponding
receive packet ready interrupt enable bit has been
asserted.
(EOP: End of packet)
After the number of bytes in the receive FIFO data
(EPnFIFO) indicated by the corresponding receive byte
count register (EPnRXCNT) has been read, write a “1” into
the receive packet ready bit of the corresponding EP status
register (EPnSTAT). (This status is reset when a '1' is
written in this bit.)
Receive packet ready
interrupt generation
End of receive packet ready
interrupt
Local MCU (firmware)
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