
ML674001 Series/ML675001 Series User’s Manual
Chapter 8
Interrupt Controller
8-1
Chapter 8
Interrupt Controller
8.
8.1
Overview
This LSI has an 8-level priority, individually maskable, highly configurable interrupt controller.
The interrupt
controller features are designed to provide flexibility to software programmer for designing an efficient interrupt
handling routine.
The interrupt controller is connected to the nFIQ (fast interrupt request) and nIRQ (interrupt request) inputs of
the ARM7TDMI processor.
The processor nFIQ is only asserted in response to an external FIQ request through
the pin EFIQ_N.
The processor nIRQ is asserted in response to interrupt requests from internal peripherals or
external pins EXINT0-EXINT3.
In total, the interrupt controller supports 23 interrupt (IRQ) sources and 1 fast interrupt (FIQ) source.
Nineteen
of the interrupt sources are coming from internal peripherals such as DMA, UART, SIO, etc.
The other four
interrupt sources are from external inputs; EXINT0, EXINT1, EXINT2, and EXINT3.
In addition it supports
one external fast interrupt (FIQ) source through the pin EFIQ_N.
The 8-level priority control feature allows the customer to define the interrupt priority level for the different
interrupt sources.
External interrupt sources can be configured to be edge triggered or level triggered. Also, for edge triggered
devices, the customer can configure the interrupt controller to trigger either on the negative or positive edge of
the input.
The FIQ is falling edge triggered.
The following is an overview of main features of the interrupt controller:
Features
One fast interrupt (FIQ) source (external)
27 interrupt (IRQ) sources (external and internal)
Independent masking for each FIQ and IRQ source
Independent interrupt priority level settings for each IRQ source
Priority control blocking IRQ requests with priority levels at or below those for interrupt requests currently
being processed
Choice of level or edge sensing for external IRQ sources EXINT0 to EXINT3 (nIR22, nIR26, nIR28, and
nIR31).
Conversion of external interrupt requests to wake-up requests for restarting the clock and thus waking the
LSI from STANDBY mode