參數(shù)資料
型號(hào)： ML9352
廠(chǎng)商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 128-Channel Organic EL Driver with Built-in RAM
中文描述： 128通道有機(jī)EL帶內(nèi)置驅(qū)動(dòng)器在RAM
文件頁(yè)數(shù)： 23/53頁(yè)
文件大?。?/td> 302K
代理商： ML9352
PEDL9352-01
OKI Semiconductor
ML9352
23/53
Reset circuit
This LSI goes into the initialized condition when the
RES
input goes to the “L” level. The initialized condition
consists of the following conditions.
(1)
Display OFF
(2)
Normal display mode
(3)
ADC Select: Forward (ADC command D0 = “L”)
(4)
The registers and data in the serial interface are cleared.
(5)
Read-modify-write: OFF
(6)
Scroll start line is set to line 1.
(7)
The column address is address 0.
(8)
The write address is 00H.
(9)
Common output state: Normal
(10)
A fixed display line is not set.
(11)
The number of display lines is 32.
(12)
The anode pulse width adjustment is 0/256.
(13)
The reverse voltage pulse width adjustment is 16/256.
(14)
Applied reverse voltage setting OFF
(15)
The cathode drive system is set to “Low during discharge” and “High during other than discharge in
non-selection mode”.
(16)
The anode drive system is set to “Low during display OFF”.
(17)
The anode output current adjusting external resistor is R
EL1
.
(18)
Static OFF.
On the other hand, when the reset command is used, only the conditions (5) to (18) above are set.
As is shown in the “MPU Interface (example for reference)”, the
RES
pin is connected to the Reset pin of the MPU
and the initialization of this LSI is made simultaneously with the resetting of the MPU. This LSI always has to be
reset using the
RES
pin at the time the power is switched ON. Also, excessive current can flow through this LSI
when the control signal from the MPU is in the Hi-Z state. It is necessary to take measures to ensure that the
control signal from the MPU does not go into the Hi-Z state after the power has been switched ON. During the
period when
RES
= “L”, although the oscillator circuit is operating, the display timing generator would have
stopped and the CL pin would have been tied to the “H” level. There is no effect on the pins D0 to D7.
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