
PEDL9352-01
OKI Semiconductor
ML9352
30/53
Anode drive set (Write)
This command is used to select an output state of the anode drive circuit during display-OFF condition.
Anode output state
A0
D7
Low
0
1
High impedance
0
1
Anode pulse width adjustment (Write)
This command specifies the output pulse width of the anode driver outputs (SEG0 to SEG127). This allows a
luminance of the organic EL panel to be set.
This command is used together with a pair of the anode pulse width adjustment set mode command and the anode
pulse width adjustment register set command. Be sure to use these paired commands sequentially.
Anode pulse width adjustment set mode (Write)
The anode pulse width adjustment register set command is enabled by setting this command. When the anode
pulse width adjustment set mode is set, commands other than the anode pulse width adjustment register set
command cannot be used. This state is released by setting anode pulse width adjustment data to the register.
A0
D7
D6
D5
D4
0
1
0
0
0
Anode pulse width adjustment register set (Write)
The duty of anode driver output pulse width is set between 0/256 and 240/256 by setting 8-bit data to the anode
pulse width adjustment register using this command.
If 8-bit data (D7 to D0) is set with F0h to FFh, the output pulse width (duty) becomes 240/256.
When the anode pulse width adjustment register is set by inputting this command, the anode pulse width
adjustment set mode is released.
Output pulse width
(Duty)
0/256
0
0
0
1/256
0
0
0
2/256
0
0
0
239/256
0
1
1
240/256
0
1
1
240/256
0
1
1
Reverse voltage pulse width adjustment (Write)
This command specifies the pulse width for the reverse voltage applying duration (applying reverse voltage makes
all anode outputs low and all cathode outputs high). This command is used together with a pair of the reverse
voltage pulse width adjustment set mode command and the reverse voltage pulse width adjustment register set
command. Be sure to use these paired commands sequentially.
D6
0
0
D5
1
1
D4
0
0
D3
1
1
D2
0
0
D1
0
0
D0
0
1
D3
0
D2
0
D1
0
D0
1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1