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參數(shù)資料
| 型號(hào)： | ML9352 |
| 廠(chǎng)商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 128-Channel Organic EL Driver with Built-in RAM |
| 中文描述： | 128通道有機(jī)EL帶內(nèi)置驅(qū)動(dòng)器在RAM |
| 文件頁(yè)數(shù)： | 27/53頁(yè) |
| 文件大?。?/td> | 302K |
| 代理商： | ML9352 |
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PEDL9352-01
OKI Semiconductor
ML9352
27/53
Column address set (Write)
This command specifies the column address of the display data RAM. The column address is specified by
successively writing the upper 4 bits and the lower 4 bits. Since the column address is automatically incremented
(by +1) every time the display data RAM is accessed, the MPU can read or write the display data continuously.
The incrementing of the column address is stopped at the address 7FH.
A0
D7
D6
Upper bits
0
0
0
Lower bits
0
0
0
Column address
a7
a6
a5
00H
0
0
0
01H
0
0
0
02H
0
0
0
7EH
0
1
1
7FH
0
1
1
Status read (Read)
A0
D7
D6
D5
D4
0
BUSY
ADC
ON/OFF
RESET
BUSY
When BUSY is ‘1’, it indicates that the internal operations are being made or the LSI is being
reset. Although no command is accepted until BUSY becomes ‘0’, there is no need to check
this bit if the cycle time can be satisfied.
ADC
This bit indicates the relationship between the column address and the segment driver.
0: Reverse (SEG127
→
SEG0; column address 0H
→
7FH)
1: Forward (SEG0
→
SEG127; column address 0H
→
7FH)
(Opposite to the polarity of the ADC command.)
ON/OFF
This bit indicates the ON/OFF state of the display. (Opposite to the polarity of the display
ON/OFF command.)
0: Display ON
1: Display OFF
RESET
This bit indicates that the LSI is being reset due to the
RES
signal or the reset command.
0: Operating state
1: Being reset
Display data write (Write)
This command writes an 8-bit data at the specified address of the display data RAM. Since the column address is
automatically incremented (by +1) after writing the data, the MPU can write the display data to the display data
RAM continuously.
A0
D7
D6
D5
D4
1
Write data
D5
0
0
D4
1
0
D3
a7
a3
D2
a6
a2
D1
a5
a1
D0
a4
a0
a4
0
0
0
1
1
a3
0
0
0
1
1
a2
0
0
0
1
1
a1
0
0
1
1
1
a0
0
1
0
0
1
D3
0
D2
0
D1
0
D0
0
D3
D2
D1
D0
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