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參數(shù)資料
| 型號(hào)： | ML9352 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 128-Channel Organic EL Driver with Built-in RAM |
| 中文描述： | 128通道有機(jī)EL帶內(nèi)置驅(qū)動(dòng)器在RAM |
| 文件頁(yè)數(shù)： | 6/53頁(yè) |
| 文件大?。?/td> | 302K |
| 代理商： | ML9352 |
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PEDL9352-01
OKI Semiconductor
ML9352
6/53
FUNCTIONAL DESCRIPTION
MPU Interface
Selection of interface type
The ML9352 carries out data transfer using either the 8-bit bi-directional data bus (D7 to D0) or the serial data
input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 1 by setting
the
P
/S pin to the “H” or the “L” level.
Table 1
P
/S
CS1
CS2
A0
RD
L: Parallel input
CS1
CS2
A0
RD
H: Serial input
CS1
CS2
A0
—
A dash (—) indicates that the pin can be tied to the “H” or the “L” level.
Parallel interface
When the parallel interface is selected, (
P
/S = “L”), it is possible to connect this LSI directly to the MPU bus of
either an 80-series MPU or a 68-series MPU as shown in Table 2 depending on whether the pin C86 is set to “H” or
“L”.
Table 2
C86
Type
CS1
H
H: 68-Series MPU bus
CS1
L
L: 80-Series MPU bus
CS1
The data bus signals are identified as shown in Table 3 below depending on the combination of the signals A0,
RD
(E), and
WR
(R/
W
) of Table 2.
Table 3
Common
A0
Display data read
1
Display data write
1
Status read
0
Control data write (command)
0
WR
WR
—
C86
C86
—
D7
D7
SI
D6
D6
SCL
D5 to D0
D5 to D0
(HZ)
CS2
CS2
CS2
A0
A0
A0
RD
E
RD
WR
R/
W
WR
D7 to D0
D7 to D0
D7 to D0
68-Series
R/
W
1
0
1
0
80-Series
RD
WR
0
1
0
1
1
0
1
0
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