參數(shù)資料
型號: ML9352
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 128-Channel Organic EL Driver with Built-in RAM
中文描述: 128通道有機EL帶內(nèi)置驅(qū)動器在RAM
文件頁數(shù): 45/53頁
文件大小: 302K
代理商: ML9352
PEDL9352-01
OKI Semiconductor
ML9352
45/53
(V
DDA
= V
DDL
= 2.7 to 4.5 V, V
SSA
= V
SSL
= 0 V, Tjop = –40 to +125°C)
Symbol
Condition
t
AH8
t
AW8
t
CYC8
t
CCLW
t
CCLR
t
CCHW
t
CCHR
t
DS8
t
DH8
t
ACC8
t
OH8
Parameter
Min.
0
0
400
60
120
60
60
40
15
10
Max.
140
100
Unit
Address hold time
Address setup time
System cycle time
Control “L” pulse width (
WR
)
Control “L” pulse width (
RD
)
Control “H” pulse width (
WR
)
Control “H” pulse width (
RD
)
Data setup time
Data hold time
RD
access time
Output disable time
CL = 100 pF
ns
Note 1: The input signal rise and fall times are specified as 15 ns or less.
When using the system cycle time for fast speed, the specified values are (tr + tf)
(t
CYC8
t
CCLW
– t
CCHW
) or (tr + tf)
(t
CYC8
– t
CCLR
– t
CCHR
).
Note 2: All timings are specified taking the levels of 20% and 80% of V
DD
as the reference.
Note 3: The values of t
CCLW
and t
CCLR
are specified during the overlapping period of
CS1
at “L” (CS2 =
“H”) and the “L” levels of
WR
and
RD
, respectively.
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