參數(shù)資料
型號: MPC5200B
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: SDRAM/DDR Memory Controller
中文描述: 內存/ DDR存儲器控制器
文件頁數(shù): 23/78頁
文件大?。?/td> 629K
代理商: MPC5200B
Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 1
Freescale Semiconductor
23
Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
MEM_CLK
MDQS (Data Strobe)
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Active
NOP
READ
NOP
NOP
NOP
NOP
NOP
t
hold
Row
Column
MBA (Bank Selects)
t
valid
t
hold
t
valid
t
hold
t
valid
t
data_valid_min
t
data_valid_max
Read Data
t
data_sample_min
t
data_sample_max
Sample Window
MDQ (Data)
MDQS (Data Strobe)
t
data_valid_min
t
data_valid_max
Read Data
t
data_sample_min
t
data_sample_max
Sample Window
Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data
Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the vaild MDQS signal
Sample
position
A
Sample
position
B
0.5 *
t
MEM_CLK
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