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參數(shù)資料
| 型號： | MPC5553MZP132 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 62/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU MPC5553 REV A 416-PBGA |
| 產(chǎn)品培訓(xùn)模塊： | MPC55xx PitchPak Family |
| 標(biāo)準(zhǔn)包裝： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 132MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 220 |
| 程序存儲器容量： | 1.5MB（1.5M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 416-BBGA |
| 包裝： | 托盤 |
| 配用： | MPC5553EVBISYS-ND - KIT EVAL ISYSTEMS MPC5553 MPC5553EVBGHS-ND - KIT EVAL GREEN HILLS SOFTWARE MPC5553EVB-ND - KIT EVAL MPC5553MZP132 MPC5553EVBE-ND - BOARD EVAL FOR MPC5553 |
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Revision History for the MPC5553 Data Sheet
MPC5553 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
65
Table 10 (I/O Pad Average DC Current (TA = TL to TH)) I/O Pad Average DC Current: Added (TA = TL – TH)
Table 11 (VDD33 Pad Average DC Current (TA = TL to TH)) VDD3 Pad Average DC Current: Added (TA = TL – TH)
Table 12 (FMPLL Electrical Specifications) FMPLL Electrical Characteristics:
Spec 1, footnote 1 in column 2: ‘PLL reference frequency range’: Added that reads ‘Nominal crystal and external
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
Spec 21, column 2: Changed fref_crystal to fref in ICO frequency equation, and
added the same equation but substituted fref_ext for fref for the external reference clock, giving:
fico = [ fref_crystal (MFD + 4) ] (PREDIV + 1)
fico = [ fref_ext (MFD + 4) ] (PREDIV + 1)
Spec 21: Changed column 5 from ‘fSYS’ MHz’ to: ‘fMAX’.
Spec 22: Changed column 4, Max Value from fMAX to 20, and added footnote 17 to read, ‘Maximum value for
dual controller (1:1) mode is (fMAX 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
Table 13 (eQADC Conversion Specifications (TA = TL to TH)) eQADC Conversion Specifications: Added (TA = TL – TH) to the
table title.
Table 14 (Flash Program and Erase Specifications (TA = TL to TH)) Flash Program and Erase Specifications:
Added (TA = TL – TH) to the table title.
Specs 9 and 10: Changed typical values for the H7Fa Flash pre-program and erase times:
-- 48 KB: from 435 to 345
-- 64 KB: from 525 to 415
Spec 8, 128KB block pre-program and erase time:
-- Typical column values from 675 to 500.
-- Initial Max column from 1800 to 1250.
-- Max column values from 15,000 to 7,500.
Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
Footnote 2: Changed from: ‘Initial factory condition:
100program/erase cycles, 25 oC, typical supply voltage,
80 MHz minimum system frequency.‘To: ‘Initial factory condition:
100program/erase cycles, 25 oC, using a
typical supply voltage measured at a minimum system frequency of 80 MHz.’
Table 15 (Flash EEPROM Module Life (TA = TL to TH)) Flash EEPROM Module Life:
Replaced (Full Temperature Range) with (TA = TL – TH) in the table title.
Spec 1b, Min. column value changed from 10,000 to 1,000.
Table 16 (FLASH_BIU Settings vs. Frequency of Operation) FLASH BIU Settings vs. Frequency of Operations:
‘Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist. Use entries from
the same row in this table.’
Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column header.
Deleted the x-refs in the ‘DPFEN’ column for the rows.
Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
Deleted the x-refs in the ‘IPFEN’ column for the rows.
Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column header.
Deleted the x-refs in the ‘PFLIM’ column for the rows.
Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
Deleted the x-refs in the ‘BFEN’ column for the rows.
Changed footnotes 1, 5, and 6 to become footnotes 5, 6, and 7
-- footnote 5
82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM).
-- footnote 6 102 MHz parts allow for 100 MHz system clock + 2% FM.
-- footnote 7 132 MHz parts allow for 128 MHz system clock + 2% FM.
Table 33. Table and Figure Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5553MZP132R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5553MZP80 | 制造商:Freescale Semiconductor 功能描述:MPC5553 416 - SNPB - Trays |
| MPC5553MZP80R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5553MZQ112 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5553MZQ112R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
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