MOTOROLA
Chapter 7. Reset
7-13
Reset Configuration
3
BDIS
Boot Disable — If the BDIS bit is set, then memory controller is not activated after reset. If it is
cleared then the memory controller bank 0 is active immediately after reset such that it matches
any addresses. If a write to the OR0 register occurs after reset this bit definition is ignored. The
default value is that the memory controller is enabled to control the boot with the CS[0] pin. See
0 Memory controller bank 0 is active and matches all addresses immediately after reset
1 Memory controller is not activated after reset.
4:5
BPS
Boot Port Size — This field defines the port size of the boot device on reset (BR0[PS]). If a write
to the OR0 register occurs after reset this field definition is ignored. See
Table 10-5 and
00 32-bit port (default)
01 8-bit port
10 16-bit port
11 Reserved
6:8
—
Reserved. These bits must not be high in the reset configuration word.
9:10
(SIUMCR),” for this field definition. The default value is that these pins function as: VFLS[0:1], BI,
11
—
Reserved. 1
12
ATWC
Address Type Write Enable Configuration — The default value is that these pins function as WE
pins.
0WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
13:14
EBDF
External Bus Division Factor — This field defines the initial value of the external bus frequency.
The default value is that CLKOUT frequency is equal to that of the internal clock (no division). See
15
—
Reserved. This bit must be 0 in the reset configuration word.
16
PRPM
Peripheral Mode Enable — This bit determines if the chip is in peripheral mode. A detailed
description is in
Table 6-13 The default value is no peripheral mode enabled.
17:18
SC
Single Chip Select — This field defines the mode of the MPC565/MPC566.
00 Extended chip, 32 bits data
01 Extended chip, 16 bits data
10 Single chip and show cycles (address)
11 Single chip
19
ETRE
Exception Table Relocation Enable — This field defines whether the Exception Table Relocation
feature in the BBC is enabled or disabled; The default state for this field is disabled. For more
20
FLEN
Flash Enable — This field determines whether the on-chip flash memory is enabled or disabled
out of reset. The default state is disabled, which means that by default, the boot is from external
0 Flash disabled — boot is from external memory
1 Flash enabled
21
EN_
COMP 2
Enable Compression — This bit enables the operation of the MPC565/MPC566 with compressed
code. The default state is disabled. See
Table 4-4.Table 7-5. RCW Bit Descriptions (continued)
Bit(s)
Name
Description