MOTOROLA
Chapter 13. Queued Analog-To-Digital Converter (QADC64E)
13-11
Programming the QADC64E Registers
13.2.1.1 Low Power Stop Mode
When the STOP bit in the QADCMCR is set, the QADC64E clock (QCLK) which clocks
the A/D converter, is disabled and the analog circuitry is powered down. This results in a
static, low power consumption, idle condition. The stop mode aborts any conversion
sequence in progress. Because the bias currents to the analog circuits are turned off in stop
mode, the QADC64E requires some recovery time (T
SR
Characteristics”) to stabilize the analog circuits after the stop enable bit is cleared.
In stop mode:
BIU state machine and logic do not shut down
The RAM is not reset and is not accessible
The module configuration register (QADCMCR), the interrupt register
(QADCINT), and the test register (QADCTEST) are fully accessible and are not
reset
The data direction register (DDRQA), port data register (PORTQA/PORTQB), and
control register 0 (QACR0) are not reset and are read-only accessible
Control register 1 (QACR1), control register 2 (QACR2), and the status registers
(QASR0 and QASR1) are reset and are read-only accessible
In addition, the periodic/interval timer is held in reset during stop mode
If the STOP bit is clear, stop mode is disabled.
13.2.1.2 Freeze Mode
Freeze mode occurs when the background debug mode is enabled in the device integration
module and a breakpoint is encountered. This is indicated by the assertion of the internal
FREEZE line on the IMB. The FRZ bit in the QADCMCR determines whether or not the
QADC64E responds to an IMB internal FREEZE signal assertion. Freeze is very useful
when debugging an application.
When the internal FREEZE signal is asserted and the FRZ bit is set, the QADC64E finishes
any conversion in progress and then freezes. Depending on when the FREEZE signal is
asserted, there are three possible queue "freeze" scenarios:
When a queue is not executing, the QADC64E freezes immediately
When a queue is executing, the QADC64E completes the conversion in progress and
then freezes
If, during the execution of the current conversion, the queue operating mode for the
active queue is changed, or a queue 2 abort occurs, the QADC64E freezes
immediately
When the QADC64E enters the freeze mode while a queue is active, the current CCW
location of the queue pointer is saved.