- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45352 > MPC603RZT266TX (MOTOROLA INC) 32-BIT, 266 MHz, RISC PROCESSOR, PBGA255 PDF資料下載
參數(shù)資料
| 型號： | MPC603RZT266TX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA255 |
| 封裝： | 23 X 23 MM, 2.60 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-255 |
| 文件頁數(shù)： | 36/36頁 |
| 文件大小： | 440K |
| 代理商： | MPC603RZT266TX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁
PID7t-603e Hardware Specifications
9
Electrical and Thermal Characteristics
Figure 1 provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
1.4.2.2 Input AC Specications
Table 8 provides the input AC timing specications for the PID7t-603e as dened in Figure 2 and Figure 3.
Table 8. Input AC Timing Specifications1
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj 105° C
Num
Characteristic
200, 266, 300 MHz
Unit
Notes
Min
Max
10a
Address/data/transfer attribute inputs valid to SYSCLK (input setup)
2.5
—
ns
2
10b
All other inputs valid to SYSCLK (input setup)
3.5
—
ns
3
10c
Mode select inputs valid to HRESET (input setup)
(for DRTRY, QACK and TLBISYNC)
8—
tsysclk
4, 5, 6, 7
11a
SYSCLK to address/data/transfer attribute inputs invalid (input hold)
1.0
—
ns
2
11b
SYSCLK to all other inputs invalid (input hold)
1.0
—
ns
3
11c
HRESET to mode select inputs invalid (input hold)
(for DRTRY, QACK, and TLBISYNC)
0
—
ns
4, 6, 7
Notes:
1. Input specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge
of the input SYSCLK. Input and output timings are measured at the pin.
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4], TC[0–1], TBST,
TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other input signals are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY,
TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specication is for conguration mode only. Also note that HRESET must be held asserted for a minimum of 255
bus clocks after the PLL-relock time during the power-on reset sequence.
VM
CVil
CVih
SYSCLK
2
3
4
VM = Midpoint Voltage (1.4 V)
4
1
VM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC603RZT133LX | 32-BIT, 133 MHz, RISC PROCESSOR, PBGA255 |
| MPC603RRX166TX | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| MPC603RRX233LX | 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255 |
| MPC603RRX100LX | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| MPC603RRX133LX | 32-BIT, 133 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC604E | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PowerPC 604e-TM RISC Microprocessor Technical Summary |
| MPC6071 | 制造商:International Rectifier 功能描述: |
| MPC616 | 制造商:Hammond Manufacturing 功能描述:6" X 16" MAGNET PANEL COVER |
| MPC-628-011B | 制造商:FCI 功能描述: |
| MPC628726C | 制造商:FCI 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。