參數(shù)資料
型號: MPC755
廠商: Motorola, Inc.
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 28/56頁
文件大小: 1652K
代理商: MPC755
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
28
Freescale Semiconductor
Pinout Listings
Table 15
provides the pinout listing for the MPC755, 360 PBGA and CBGA packages.
VOLTDET
F3
High
Output
6
Notes:
1. OV
DD
supplies power to the processor bus, JTAG, and all control signals; and V
DD
supplies power to the processor core and the PLL (after
filtering to become AV
DD
). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL
pin configuration of
Table 2
and the voltage supplied. For actual recommended value of V
in
or supply voltages, see
Table 3
.
2. These are test signals for factory use only and must be pulled up to OV
DD
for normal machine operation.
3. This pin must be pulled up to OV
DD
for proper operation of the processor interface. To allow for future I/O voltage changes, provide the option
to connect BVSEL independently to either OV
DD
or GND.
4. Uses 1 of 15 existing no connects in the MPC740, 255 BGA package.
5. Internal pull-up on die.
6. Internally tied to GND in the MPC745, 255 BGA package to indicate to the power supply that a low-voltage processor is present. This signal
is not a power supply input.
Caution:
This differs from the MPC755, 360 BGA package.
Table 15. Pinout Listing for the MPC755, 360 BGA Package
Signal Name
Pin Number
Active
I/O
I/F Voltage
1
Notes
A[0:31]
A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3,
G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3,
H3, J2, J6, K3, K2, L2
High
I/O
OV
DD
AACK
N3
Low
Input
OV
DD
ABB
L7
Low
I/O
OV
DD
AP[0:3]
C4, C5, C6, C7
High
I/O
OV
DD
ARTRY
L6
Low
I/O
OV
DD
AV
DD
A8
2.0 V
BG
H1
Low
Input
OV
DD
BR
E7
Low
Output
OV
DD
BVSEL
W1
High
Input
OV
DD
3, 5, 6
CI
C2
Low
Output
OV
DD
CKSTP_IN
B8
Low
Input
OV
DD
CKSTP_OUT
D7
Low
Output
OV
DD
CLK_OUT
E3
Output
OV
DD
DBB
K5
Low
I/O
OV
DD
DBDIS
G1
Low
Input
OV
DD
DBG
K1
Low
Input
OV
DD
DBWO
D1
Low
Input
OV
DD
Table 14. Pinout Listing for the MPC745, 255 PBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Voltage
1
Notes
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