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參數(shù)資料
| 型號(hào)： | MPC755CRX400LE |
| 廠商： | Motorola, Inc. |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 1652K |
| 代理商： | MPC755CRX400LE |
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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
16
Freescale Semiconductor
Electrical and Thermal Characteristics
SYSCLK to ARTRY high impedance after precharge
t
KHARPZ
—
2
t
sysclk
2, 3, 5
Notes:
1. Revisions prior to Rev. 2.8 (Rev. E) were limited in performance and did not conform to this specification. For more information, refer to
Section 10.2, “Part Numbers Not Fully Addressed by This Document
.”
2. Guaranteed by design and characterization.
3. t
sysclk
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of SYSCLK to
compute the actual time duration (in ns) of the parameter in question.
4. Per the 60x bus protocol, TS, ABB, and DBB are driven only by the currently active bus master. They are asserted low, then precharged high
before returning to high-Z as shown in
Figure 6
. The nominal precharge width for TS, ABB, or DBB is 0.5
×
t
sysclk
, that is, less than the
minimum t
sysclk
period, to ensure that another master asserting TS, ABB, or DBB on the following clock will not contend with the precharge.
Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge. The high-Z behavior is
guaranteed by design.
5. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention
is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then
go to high-Z for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for
ARTRY is 1.0 t
sysclk
; that is, it should be high-Z as shown in
Figure 6
before the first opportunity for another master to assert ARTRY. Output
valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge. The high-Z and precharge behavior is
guaranteed by design.
6. MCP and SRESET must be held asserted for a minimum of two bus clock cycles; INT and SMI should be held asserted until the exception
is taken; CKSTP_IN must be held asserted until the system has been reset. See the
MPC750 RISC Microprocessor Family User’s Manual
for more information.
Table 10. Processor Bus AC Timing Specifications
1
(continued)
At recommended operating conditions (see
Table 3
)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
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