參數(shù)資料
型號(hào): MPC755CRX400LE
廠商: Motorola, Inc.
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁(yè)數(shù): 19/56頁(yè)
文件大?。?/td> 1652K
代理商: MPC755CRX400LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
19
Electrical and Thermal Characteristics
Figure 7. L2CLK_OUT Output Timing Diagram
4.2.4
L2 Bus AC Specifications
Table 12
provides the L2 bus interface AC timing specifications for the MPC755 as defined in
Figure 8
and
Figure 9
for the loading conditions described in
Figure 10
.
Table 12. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (see
Table 3
)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L2SYNC_IN rise and fall time
t
L2CR
, t
L2CF
1.0
ns
1
Setup times: Data and parity
t
DVL2CH
1.2
ns
2
Input hold times: Data and parity
t
DXL2CH
0
ns
2
Valid times:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
t
L2CHOV
3.1
3.2
3.3
3.7
ns
3, 4
Output hold times:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
t
L2CHOX
0.5
0.7
0.9
1.1
ns
3
VM = Midpoint Voltage (L2OV
DD
/2)
L2CLK_OUTA
L2CLK_OUTB
L2 Differential Clock Mode
L2 Single-Ended Clock Mode
L2SYNC_OUT
t
L2CLK
t
CHCL
L2CLK_OUTA
VM
t
L2CR
t
L2CF
VM
VM
VM
L2CLK_OUTB
VM
VM
VM
VM
VM
t
L2CLK
L2SYNC_OUT
VM
VM
VM
VM
VM
VM
VM
VM
t
L2CSKW
t
CHCL
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