參數(shù)資料
型號(hào)： MPC755CRX400LE
廠商： Motorola, Inc.
英文描述： RISC Microprocessor Hardware Specifications
中文描述： RISC微處理器硬件規(guī)格
文件頁(yè)數(shù)： 39/56頁(yè)
文件大小： 1652K
代理商： MPC755CRX400LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
39
System Design Information
Figure 21
shows the PLL power supply filter circuit.
Figure 21. PLL Power Supply Filter Circuit
8.3
Decoupling Recommendations
Due to the MPC755 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC755 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC755 system, and the MPC755 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each V
DD
, OV
DD
, and L2OV
DD
pin of the MPC755. It is also recommended that these decoupling capacitors receive their power from separate V
DD
,
(L2)OV
DD
, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 μF. Only ceramic SMT (surface mount technology) capacitors
should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along
the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the
V
DD
, L2OV
DD
, and OV
DD
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors:100–330 μF (AVX TPS tantalum or Sanyo OSCON).
8.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level
through a resistor. Unused active low inputs should be tied to OV
DD
. Unused active high inputs should be connected
to GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD
, OV
DD
, L2OV
DD
, and GND pins of the MPC755.
Note that power must be supplied to L2OV
DD
even if the L2 interface of the MPC755 will not be used; it is
recommended to connect L2OV
DD
to OV
DD
and L2VSEL to BVSEL if the L2 interface is unused. (This
requirement does not apply to the MPC745 since it has neither an L2 interface nor L2OV
DD
pins.)
8.5
Output Buffer DC Impedance
The MPC755 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure Z
0
, an
external resistor is connected from the chip pad to (L2)OV
DD
or GND. Then, the value of each resistor is varied
until the pad voltage is (L2)OV
DD
/2 (see
Figure 22
).
The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When
data is held low, SW2 is closed (SW1 is open), and R
N
is trimmed until the voltage at the pad equals (L2)OV
DD
/2.
V
DD
AV
DD
(or L2AV
DD
)
10
2.2 μF
2.2 μF
GND
Low ESL Surface Mount Capacitors
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