參數(shù)資料
型號(hào): MPC755CRX400LE
廠商: Motorola, Inc.
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 21/56頁
文件大?。?/td> 1652K
代理商: MPC755CRX400LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
21
Electrical and Thermal Characteristics
Figure 8
shows the L2 bus input timing diagrams for the MPC755.
Figure 8. L2 Bus Input Timing Diagrams
Figure 9
shows the L2 bus output timing diagrams for the MPC755.
Figure 9. L2 Bus Output Timing Diagrams
Figure 10
provides the AC test load for L2 interface of the MPC755.
Figure 10. AC Test Load for the L2 Interface
4.2.5
IEEE 1149.1 AC Timing Specifications
Table 13
provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in
Figure 12
through
Figure 15
.
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK)
1
At recommended operating conditions (see
Table 3
)
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
f
TCLK
0
16
MHz
TCK cycle time
t
TCLK
62.5
ns
TCK clock pulse width measured at 1.4 V
t
JHJL
31
ns
TCK rise and fall times
t
JR
, t
JF
0
2
ns
L2SYNC_IN
L2 Data and Data
Parity Inputs
VM
VM = Midpoint Voltage (L2OV
DD
/2)
t
DVL2CH
t
DXL2CH
t
L2CR
t
L2CF
L2SYNC_IN
All Outputs
VM
VM = Midpoint Voltage (L2OV
DD
/2)
t
L2CHOV
t
L2CHOX
VM
L2DATA BUS
t
L2CHOZ
Output
Z
0
= 50
L2OV
DD
/2
R
L
= 50
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