參數(shù)資料
型號(hào): MPC8377E-RDBA
廠商: Freescale Semiconductor
文件頁數(shù): 39/127頁
文件大小: 0K
描述: BOARD REF DES MPC8377 REV 2.1
設(shè)計(jì)資源: MPC8379E-RDB Ref Design Guide
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8377E
所含物品: 板,CD
相關(guān)產(chǎn)品: MPC8378EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
MPC8378EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
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MPC8378EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8379EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
MPC8379EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8379EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
MPC8379EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8377EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8377EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
19
6.2
DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR1 and DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
This table provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V.
This table provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
V
Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
V
Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Note
Controller skew for MDQS-MDQ/MECC/MDM
400 MHz data rate
333 MHz data rate
266 MHz data rate
tCISKEW
–500
–750
500
750
ps
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that
will be captured with MDQS
n. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = ±[T/4 – |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the
absolute value of tCISKEW.
3. This specification applies only to DDR2 interface.
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