參數(shù)資料
型號: MPC8377E-RDBA
廠商: Freescale Semiconductor
文件頁數(shù): 58/127頁
文件大?。?/td> 0K
描述: BOARD REF DES MPC8377 REV 2.1
設(shè)計資源: MPC8379E-RDB Ref Design Guide
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8377E
所含物品: 板,CD
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更多...
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
36
Freescale Semiconductor
10.2
Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface of the device when in PLL
enable mode.
Table 38. Local Bus DC Electrical Characteristics (LBVDD =1.8 V)
At recommended operating conditions with LBVDD = 1.8 V.
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage 1.8 V
LBVDD
1.71
1.89
V
Output high voltage
IOH = –1.0 mA
LBVDD = Min
VOH
LBVDD – 0.45
V
Output low voltage
IOL = 1.0 mA
LBVDD = Min
VOL
—0.45
V
Input high voltage
LBVDD = Min
VIH
0.65
× LBVDD
LBVDD + 0.3
V
Input low voltage
LBVDD = Min
VIL
–0.3
0.35
× LBVDD
V
Input high current
VIN
1 = LBV
DD
IIH
—10
μA
Input low current
VIN
1 = GND
IIL
–10
μA
Table 39. Local Bus General Timing Parameters—PLL Enable Mode
Parameter
Symbol1
Min
Max
Unit
Note
Local bus cycle time
tLBK
7.5
15
ns
Input setup to local bus clock (except LUPWAIT/LGTA)tLBIVKH
1.5
ns
Input hold from local bus clock
tLBIXKH
1.0
ns
LUPWAIT/LGTA input setup to local bus clock
tLBIVKH1
1.5
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
ns
Local bus clock to LALE rise
tLBKHLR
—4.5
ns
Local bus clock to output valid (except LALE)
tLBKHOV
—4.5
ns
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