tCLK_DELAY
參數(shù)資料
型號(hào): MPC8377E-RDBA
廠商: Freescale Semiconductor
文件頁數(shù): 71/127頁
文件大?。?/td> 0K
描述: BOARD REF DES MPC8377 REV 2.1
設(shè)計(jì)資源: MPC8379E-RDB Ref Design Guide
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8377E
所含物品: 板,CD
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
48
Freescale Semiconductor
tCLK_DELAY + tIH tSFSKHOX < tSFSCKL+ tDATA_DELAY
Eqn. 5
This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of
tSFSCLKL =20 ns:
tCLK_DELAY + 5 0 < 20 + tDATA_DELAY
tCLK_DELAY < 15 + tDATA_DELAY
11.2.1.3
Full-Speed Write Combined Formula
The following equation is the combined formula to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tIH tSFSKHOX < tSFSCKL + tDATA_DELAY < tSFSCK+ tCLK_DELAY tISU tSFSKHOV
Eqn. 6
11.2.2
Full-Speed Input Path (Read)
This figure provides the data and command input timing diagram.
Figure 28. Full Speed Input Path
11.2.2.1
Full-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tDATA_DELAY + tODLY + tSFSIVKH < tSFSCK
Eqn. 7
tCLK_DELAY + tDATA_DELAY < tSFSCK tODLY tSFSIVKH tINT_CLK_DLY
Eqn. 8
tCLK_DELAY
Output from the
SD CLK at
the card pin
SD card pins
tSFSIVKH
tSFSIXKH
Driving
edge
Sampling
edge
tOH
tDATA_DELAY
tODLY
tSFSCK (clock cycle)
(MPC8377E input hold)
SD CLK at the
MPC8377E pin
Input at the
MPC8377E pins
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