Table 16 provides the DDR capacitance" />
參數(shù)資料
型號: MPC8377EWLANB
廠商: Freescale Semiconductor
文件頁數(shù): 38/127頁
文件大?。?/td> 0K
描述: ACCESS POINT/ROUTER MPC8377
標準包裝: 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
18
Freescale Semiconductor
Table 16 provides the DDR capacitance when GVDD(typ) = 2.5 V.
This table provides the current draw characteristics for MVREF.
Input low voltage
VIL
–0.3
MVREF – 0.18
V
Output leakage current
IOZ
–50
50
μA4
Output high current (VOUT = 1.9 V)
IOH
–15.2
mA
Output low current (VOUT = 0.38 V)
IOL
15.2
mA
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT GVDD.
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 16. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT =GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 17. Current Draw Characteristics for MVREF
Parameter
Symbol
Min
Typ
Max
Unit
Note
Current draw for MVREF
DDR1
DDR2
IMVREF
250
150
600
400
Note:
1. The voltage regulator for MVREF must be able to supply up to the stated maximum current.
2. This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.
Table 15. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V (continued)
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