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參數(shù)資料
型號： MPC8377EWLANB
廠商： Freescale Semiconductor
文件頁數(shù)： 73/127頁
文件大?。?/td> 0K
描述： ACCESS POINT/ROUTER MPC8377
標準包裝： 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
5
There are two I2C controllers. These synchronous, multi-master buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides
a seamless interface to many types of memory devices and peripherals. The memory controller is
responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As
such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash,
EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with
data signals to reduce the device pin count.
The enhanced local bus controller also includes a number of data checking and protection features, such
as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle
is terminated within a user-specified period. The local bus can operate at up to 133 MHz.
The system timers include the following features: periodic interrupt timer, real time clock, software
watchdog timer, and two general-purpose timer blocks.
1.8
Security Engine
The optional security engine is optimized to handle all the algorithms associated with IPSec,
IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto
execution units (EUs). The execution units are as follows:
Data encryption standard execution unit (DEU), supporting DES and 3DES
Advanced encryption standard unit (AESU), supporting AES
Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any
algorithm
One crypto-channel supporting multi-command descriptor chains
1.9
PCI Controller
The PCI controller includes the following features:
PCI Specification Revision 2.3 compatible
Single 32-bit data PCI interface operates at up to 66 MHz
PCI 3.3-V compatible (not 5-V compatible)
Support for host and agent modes
On-chip arbitration, supporting 5 external masters on PCI
Selectable hardware-enforced coherency
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