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| 型號(hào)： | MPC8377EWLANB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 56/127頁(yè) |
| 文件大小： | 0K |
| 描述： | ACCESS POINT/ROUTER MPC8377 |
| 標(biāo)準(zhǔn)包裝： | 1 |
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
34
Freescale Semiconductor
9.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the device.
These two figures provide the AC test load and signals for the USB, respectively.
Figure 17. USB AC Test Load
Figure 18. USB Interface Timing Diagram
Table 35. USB General Timing Parameters (ULPI Mode Only)
Parameter
Symbol 1
Min
Max
Unit
Note
USB clock cycle time
tUSCK
15
—
ns
Input setup to USB clock—all inputs
tUSIVKH
4
—
ns
Input hold to USB clock—all inputs
tUSIXKH
1
—
ns
USB clock to output valid—all outputs
tUSKHOV
—
7
ns
Output hold from USB clock—all outputs
tUSKHOX
2
—
ns
Notes:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US)
for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to the USB clock, USBDR_CLK.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered
through the component pin is less than or equal to that of the leakage current specification.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Output Signals
tUSKHOV
USBDR_CLK
Input Signals
tUSIXKH
tUSIVKH
tUSKHOX
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