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參數(shù)資料
| 型號： | MPC92433 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 1428 MHz Dual Output LVPECL Clock Synthesizer |
| 中文描述： | 1428兆赫雙輸出的LVPECL時鐘合成器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MPC92433 |
Advanced Clock Drivers Devices
Freescale Semiconductor
10
MPC92433
synthesizer, which have an immediate effect on the PLL
frequency.
Figure 3. I
2
C Mode Register Set
Figure 3
illustrates the synthesizer register set. PLL_L and
PLL_H store a PLL configuration and are fully accessible
(Read/Write) by the I
2
C bus. CMD (Write only) accepts
commands (LOAD, GET, INC, DEC) to update registers and
for direct PLL frequency changes.
Set the synthesizer frequency:
1) Write the PLL_L and PLL_H registers with a new
configuration (see
Table 13
and
Table 14
for register
maps)
2) Write the LOAD command to update the PLL dividers
by the current PLL_L, PLL_H content.
Read the synthesizer frequency:
1) Write the GET commands to update the PLL_L,
PLL_H registers by the PLL divider setting
2) Read the PLL_L, PLL_H registers through I
2
C
Change the synthesizer frequency in small steps:
1) Write the INC or DEC command to change the PLL
frequency immediately. Repeat at any time if desired.
LOAD and GET are inverse command to each other.
LOAD updates the PLL dividers and GET updates the
configuration registers. A fast and convenient way to change
the PLL frequency is to use the INC (increment M) and DEC
(decrement M) commands of the synthesizer. INC (DEC)
directly increments (decrements) the PLL-feedback divider M
and immediately changes the PLL frequency by the smallest
step G (see
Table 7
for the frequency granularity G). The INC
and DEC commands are designed for multiple and rapid PLL
frequency changes as required in frequency margining
applications. INC and DEC do not require the user to update
the PLL dividers by the LOAD command, INC and DEC do
not update the PLL_L and PLL_H registers either (use LOAD
for an initial PLL divider setting and, if desired, use GET to
read the PLL configuration). Note that the synthesizer does
not check any boundary conditions such as the VCO
frequency range. Applying the INC and DEC commands
could result in invalid VCO frequencies (VCO frequency
beyond lock range).
Register Maps
Register 0x00 (PLL_L) contains the least significant bits of
the PLL feedback divider M.
Register content:
M[7:0]
PLL feedback-divider M, bits 7–0
Register 0x01 (PLL_H) contains the two most significant
bits of the PLL feedback divider M, four bits to control the PLL
post-dividers N and the PLL pre-divider P. The bit 0 in PLL_H
register indicates the lock condition of the PLL and is set by
the synthesizer automatically. The LOCK state is a copy of
the PLL lock signal output (LOCK). A write-access to LOCK
has no effect.
Table 14. PLL_H (0x01, R/W) Register
Register content:
M[9:8]
NA[2:0]
NB
P
LOCK
PLL feedback-divider M, bits 9–8
PLL post-divider N
A
, see
Table 9
PLL post-divider N
B
, see
Table 9
PLL pre-divider P, see
Table 8
Copy of LOCK output signal (read-only)
Note that the LOAD command is required to update the
PLL dividers by the content of both PLL_L and PLL_H
registers.
Register 0xF0 (CMD) is a write-only command register.
The purpose of CMD is to provide a fast way to increase or
decrease the PLL frequency and to update the registers. The
register accepts four commands, INC (increment M), DEC
(decrement M), LOAD and GET (update registers). It is
recommended to write the INC, DEC commands only after a
valid PLL configuration is achieved. INC and DEC only affect
the M-divider of the PLL (PLL feedback). Applying INC and
DEC commands can result in a PLL configuration beyond the
specified lock range and the PLL may lose lock. The
MPC92433 does not verify the validity of any commands
such as LOAD, INC, and DEC. The INC and DEC commands
change the PLL feedback divider without updating PLL_L
and PLL_H.
Configuration Latches
I
2
C Registers
I
2
C Access
Synthesizer – PLL
N
P
M
LOAD/GET
PLL_L (R/W)
0x00
PLL_H (R/W)
0x01
CMD (W)
0xF0
Table 12. Configuration Registers
Address
Name
Content
Access
0x00
PLL_L
Least significant 8 bits of M
R/W
0x01
PLL_H
Most significant 2 bits of M, P, N
A
,
N
B
, and lock state
R/W
0xF0
CMD
Command register (write only)
W only
Table 13. PLL_L (0x00, R/W) Register
Bit
7
6
5
4
3
2
1
0
Name
M7
M6
M5
M4
M3
M2
M1
M0
Bit
7
6
5
4
3
2
1
0
Name
M9
M8
NA2
NA1
NA0
NB
P
LOCK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92433AE | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92433AER2 | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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