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參數(shù)資料
| 型號： | MPC92433 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 1428 MHz Dual Output LVPECL Clock Synthesizer |
| 中文描述： | 1428兆赫雙輸出的LVPECL時鐘合成器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 412K |
| 代理商： | MPC92433 |
Advanced Clock Drivers Devices
Freescale Semiconductor
8
MPC92433
Output Frequency Configuration
The MPC92433 is a programmable frequency source
(synthesizer) and supports an output frequency range of
42.5 – 1428 MHz. The output frequency f
OUT
is a function of
the reference frequency f
REF
and the three internal PLL
dividers P, M, and N. f
OUT
can be represented by this formula:
f
OUT
= (f
REF
÷ P) · M ÷ (N
A
,
B
) (1)
The M, N and P dividers require a configuration by the user
to achieve the desired output frequency. The output divider,
N
A,
determines the achievable output frequency range (see
Table 7
). The PLL feedback-divider M is the frequency
multiplication factor and the main variable for frequency
synthesis. For a given reference frequency f
REF
, the PLL
feedback-divider M must be configured to match the
specified VCO frequency range in order to achieve a valid
PLL configuration:
f
VCO
= (f
REF
÷ P) · M and (2)
1360
≤
f
VCO
≤
2856 (3)
The output frequency may be changed at any time by
changing the value of the PLL feedback divider M. The
smallest possible output frequency change is the synthesizer
granularity G (difference in f
OUT
when incrementing or
decrementing M). At a given reference frequency, G is a
function of the PLL pre-divider P and post-divider N:
G = f
REF
÷ (P · N
A,B
) (4)
The N
B
divider configuration determines if the output Q
B
generates a 1:1 or 2:1 frequency copy of the Q
A
output signal.
The purpose of the PLL pre-divider P is to situated the PLL
into the specified VCO frequency range f
VCO
(in combination
with M). For a given output frequency, P = 4 results in a
smaller output frequency granularity G, P = 2 results a larger
output frequency granularity G and also increases the PLL
bandwidth compared to the P = 2 setting.
The following example illustrates the output frequency
range of the MPC92433 using a 16-MHz reference
frequency.
Example Output Frequency Configuration
If a reference frequency of 16 MHz is available, an output
frequency at Q
A
of 250 MHz and a small frequency
granularity is desired, the following steps would be taken to
identify the appropriate P, M, and N configuration:
1.
Use
Table 7
to select the output divider, N
A
, that
matches the desired output frequency or frequency
range. According to
Table 7
, a target output frequency
of 250 MHz falls in the f
OUT
range of 170 to 357 MHz
and requires to set N
A
= 8
2.
Calculate the VCO frequency f
VCO
= f
OUT
· N
A
, which is
2000 MHz in this example.
3.
Determine the PLL feedback divider: M = f
VCO
÷ P.
The smallest possible output granularity in this example
calculation is 500 kHz (set P = 4). M calculates to a
value of 2000 ÷ 4 = 500.
4.
Configure the MPC92433 with the obtained settings:
M[9:0] = 0111110100b (binary number for M=500)
N
A
[2:0] = 010
P = 1
(÷8 divider, see
Table 9
)
(÷4 divider, see
Table 8
)
N
B
= 0
(f
OUT, QB
= f
OUT, QA
)
5.
Use either parallel or serial interface to apply the
setting. The I
2
C configuration bytes for this example
are:
PLL_H=01010010b and PLL_L=11110100b.
See
Table 13
and
Table 14
for register maps.
Table 7. Frequency Ranges (f
REF
=16 MHz)
f
OUT
(Q
A
) [MHz]
N
A
M
P
G [MHz]
680–1428
N
A
=2
170-357
2
4
340-714
4
2
340–714
N
A
=4
170-357
2
2
340-714
4
1
226.67–476
N
A
=6
170-357
2
1.33
340-714
4
0.66
170–357
N
A
=8
170-357
2
1
340-714
4
0.5
113.33–238
N
A
=12
170-357
2
0.66
340-714
4
0.33
85–178.5
N
A
=16
170-357
2
0.5
340-714
4
0.25
42.5–89.25
N
A
=32
170-357
2
0.25
340-714
4
0.125
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| MPC92433AE | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92433AER2 | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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