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參數(shù)資料
| 型號： | MPC92433 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 1428 MHz Dual Output LVPECL Clock Synthesizer |
| 中文描述： | 1428兆赫雙輸出的LVPECL時鐘合成器 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MPC92433 |
Advanced Clock Drivers Devices
Freescale Semiconductor
9
MPC92433
PLL Divider Configuration
Programming the MPC92433
The MPC92433 has a parallel and a serial configuration
interface. The purpose of the parallel interface is to directly
configure the PLL dividers through hardware pins without the
overhead of a serial protocol. At device startup, the device
always obtains an initial PLL frequency configuration through
the parallel interface. The parallel interface does not support
reading the PLL configuration.
The serial interface is I
2
C compatible. It allows reading and
writing devices settings by accessing internal device
registers. The serial interface is designed for host-controller
access to the synthesizer frequency settings for instance in
frequency-margining applications.
Using the Parallel Interface
The parallel interface supports write-access to the PLL
frequency setting directly through 15 configuration pins (P,
M[9:0], NA[2:0], and NB). The parallel interface must be
enabled by setting PLOAD to logic low level. During
PLOAD = 0, any change of the logical state of the P, M[9:0],
NA[2:0], and NB pins will immediately affect the internal PLL
divider settings, resulting in a change of the internal VCO-
frequency and the output frequency. The parallel interface
mode disables the I
2
C write-access to the internal registers;
however, I
2
C read-access to the internal configuration
registers is enabled.
Upon startup, when the device reset signal is released
(rising edge of the MR signal), the device reads its startup
configuration through the parallel interface and independent
on the state of PLOAD. It is recommended to provide a valid
PLL configuration for startup. If the parallel interface pins are
left open, a default PLL configuration will be loaded. After the
low-to-high transition of PLOAD, the configuration pins have
no more effect and the configuration registers are made
accessible through the serial interface.
Using the I
2
C Interface
PLOAD = 1 enables the programming and monitoring of
the internal registers through the I
2
C interface. Device
register access (write and read) is possible through the 2-wire
interface using SDA (configuration data) and SCL
(configuration clock) signals. The MPC92433 acts as a slave
device at the I
2
C bus. For further information on I
2
C it is
recommended to refer to the I
2
C bus specification (version
2.1).
PLOAD = 0 disables the I
2
C-write-access to the configura-
tion registers and any data written into the register is ignored.
However, the MPC92433 is still visible at the I
2
C interface
and I
2
C transfers are acknowledged by the device. Read-ac-
cess to the internal registers during PLOAD = 0 (parallel pro-
gramming mode) is supported.
Note that the device automatically obtains a configuration
using the parallel interface upon the release of the device
reset (rising edge of MR) and independent on the state of
PLOAD. Changing the state of the PLOAD input is not
supported when the device performs any transactions on the
I
2
C interface.
Programming Model and Register Set
The synthesizer contains two fully accessible configuration
registers (PLL_L and PLL_H) and a write-only command
register (CMD). Programming the synthesizer frequency
through the I
2
C interface requires two steps: 1) writing a valid
PLL configuration to the configuration registers and 2)
loading the registers into the PLL by an I
2
C command. The
PLL frequency is affected as a result of the second step.
This two-step procedure can be performed by a single I
2
C
transaction or by multiple, independent I
2
C transactions. An
alternative way to achieve small PLL frequency changes is to
use the increment or decrement commands of the
Table 8. Pre-PLL Divider P
P
Value
0
f
REF
÷ 2
1
f
REF
÷ 4
Table 9. Post-PLL Divider N
A
and N
B
N
A2
N
A1
N
A0
N
B
f
OUT
(Q
A
)
f
OUT
(Q
B
)
0
0
0
0
f
VCO
÷ 2
f
VCO
÷ 2
0
0
1
0
f
VCO
÷ 32
f
VCO
÷ 32
0
1
0
0
f
VCO
÷ 8
f
VCO
÷ 8
0
1
1
0
f
VCO
÷ 12
f
VCO
÷ 12
1
0
0
0
f
VCO
÷ 4
f
VCO
÷ 4
1
0
1
0
f
VCO
÷ 6
f
VCO
÷ 6
1
1
0
0
f
VCO
÷ 16
f
VCO
÷ 16
1
1
1
0
n/a
n/a
0
0
0
1
f
VCO
÷ 2
f
VCO
÷ 4
0
0
1
1
n/a
n/a
0
1
0
1
f
VCO
÷ 8
f
VCO
÷ 16
0
1
1
1
n/a
n/a
1
0
0
1
f
VCO
÷ 4
f
VCO
÷ 8
1
0
1
1
f
VCO
÷ 6
f
VCO
÷ 12
1
1
0
1
f
VCO
÷ 16
f
VCO
÷ 32
1
1
1
1
n/a
n/a
Table 10. Feedback Divider Configuration
Feedback
Divider M
9
8
7
6
5
4
3
2
1
0
Pin
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Default
0
1
1
1
1
1
0
1
0
0
Table 11. PLL Pre/Post Divider Configuration (N, P)
Post-D.
NA
2
1
0
Post-D.
NB
NB
Pre-D.
P
P
Pin
NA2
NA1
NA0
Pin
NB
Pin
P
Default
0
1
0
Default
0
Default
1
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| MPC92433AE | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92433AER2 | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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