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參數(shù)資料
| 型號(hào)： | MPC92433 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 1428 MHz Dual Output LVPECL Clock Synthesizer |
| 中文描述： | 1428兆赫雙輸出的LVPECL時(shí)鐘合成器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MPC92433 |
Advanced Clock Drivers Devices
Freescale Semiconductor
12
MPC92433
Read Mode (R/W = 1)
The configuration registers are read by the bus controller
by the initiation of a read transfer. The MPC92433 supports
read transfers immediately after the first byte without a
change in the transfer direction. Immediately after the bus
controller sends the slave address, the MPC92433
acknowledges and then sends both configuration register
PLL_L and PLL_H (back-to-back) to the bus controller. The
CMD register cannot be read. In order to read the two
synthesizer registers and the current PLL configuration
setting, the user can 1) read PLL_L, PLL_H, write the GET
command (loads the current configuration into PLL_L,
PLL_H) and read PLL_L, PLL_H again. Note that the PLL_L,
PLL_H registers and divider settings may not be equivalent
after the following cases:
a.
Writing the INC command
b.
Writing the DEC command
c.
Writing PLL_L, PLL_H registers with a new
configuration and not writing the LOAD command.
Device Startup
General Device Configuration
It is recommended to reset the MPC92433 during or
immediately after the system powers up (MR = 0). The device
acquires an initial PLL divider configuration through the
parallel interface pins M[9:0], NA[2:0], N, and P
(1)
with the
low-to-high transition of MR
(2)
. PLL frequency lock is
achieved within the specified lock time (t
LOCK
) and is
indicated by an assertion of the LOCK signal which
completes the startup procedure. It is recommended to
disable the outputs (CLK_STOPx = 0) until PLL lock is
achieved to suppress output frequency transitions. The
output frequency can be reconfigured at any time through
either the parallel or the serial interface.
Note that a PLL configuration obtained by the parallel
interface can be read through I
2
C independent on the current
programming mode (parallel or serial). Refer to the
I2C —
Register Access in Parallel Mode
section for additional
information on how to read a PLL startup configuration
through the I
2
C interface.
Starting-Up Using the Parallel Interface
The simplest way to use the MPC92433 is through the
parallel interface. The serial interface pins (SDA, SDL) and
ADDR[1:0]) can be left open and PLOAD is set to logic low.
After the release of MR and at any other time the PLL/output
frequency configuration is directly set to through the M[9:0],
NA[2:0], NB, and P pins.
Start-Up Using the Serial (I
2
C) Interface
Figure 4. Start-Up Using I
2
C Interface
Set PLOAD = 1, CLK_STOPx = L and leave the parallel
interface pins (M[9:0], NA[2:0], N, and P) open. The PLL
dividers are configured by the default configuration at the low-
to-high transition of MR. This initial PLL configuration can be
re-programmed to the final VCO frequency at any time
through the serial interface. After the PLL achieved lock at the
desired VCO frequency, enable the outputs by setting
CLK_STOPx = H. PLL lock and re-lock (after any
configuration change through M or P) is indicated by LOCK
being asserted.
Table 19. Configuration Register Read Transfer
1 bit
7 bits
1 bit
1 bit
8 bits
1 bit
8 bits
1 bit
1 bit
Start
Slave address
R/W
ACK
PLL_L
ACK
PLL_H
ACK
Stop
10110xx
(1)
1. xx = state of ADR1, ADR0 pins
1
Data
Data
Master
Master
Mast
Slave
Slave
Mast
Slave
Master
Slave
1.
The parallel interface pins M[9:0], NA[2:0], N, and P may be left open (floating). In this case the initial PLL configuration will have the default
setting of M = 500, P = 1, NA[2:0] = 010, NB = 0, resulting in an internal VCO frequency of 2000 MHz (f
ref
= 16 MHz) and an output frequency
of 250 MHz.
The initial PLL configuration is independent on the selected programming mode (PLOAD low or high)
2.
V
CC
MR
P, M, N
PLOAD
LOCK
CLK_STOPx
QA, QB
Stable & Valid
Selects I
2
C
Acquiring Lock
PLL Lock
Disabled (Low)
t
PLH
Active
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92433AE | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92433AER2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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