參數(shù)資料
型號(hào)： MPC92433
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 1428 MHz Dual Output LVPECL Clock Synthesizer
中文描述： 1428兆赫雙輸出的LVPECL時(shí)鐘合成器
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 412K
代理商： MPC92433
Advanced Clock Drivers Devices
Freescale Semiconductor
4
MPC92433
Table 2. Function Table
Control
Default
(1)
1. Default states are set by internal input pull-up or pull-down resistors of 75 k
.
2. If f
REF
= 16 MHz, the default configuration will result in an output frequency of 250 MHz.
0
1
Inputs
REF_SEL
1
Selects REF_CLK input as PLL reference clock
Selects the XTAL interface as PLL reference
clock
M[9:0]
01 1111 0100b
(2)
PLL feedback divider (10-bit) parallel programming interface
NA[2:0]
010
PLL post-divider parallel programming interface. See
Table 9
NB
0
PLL post-divider parallel programming interface. See
Table 9
P
1
PLL pre-divider parallel programming interface. See
Table 8
PLOAD
0
Selects the parallel programming interface. The
internal PLL divider settings (M, NA, NB and P) are
equal to the setting of the hardware pins. Leaving the
M, NA, NB and P pins open (floating) results in a
default PLL configuration with f
OUT
= 250 MHz. See
application/programming section.
Selects the serial (I
2
C) programming interface.
The internal PLL divider settings (M, NA, NB and
P) are set and read through the serial interface.
ADR[1:0]
00
Address bit = 0
Address bit = 1
SDA, SCL
See
Programming the MPC92433
BYPASS
1
PLL function bypassed
f
QA
=f
REF
÷ N
A
and
f
QB
=f
REF
÷ (N
A
· N
B
)
PLL function enabled
f
QA
= (f
REF
÷ P) · M ÷ N
A
and
f
QB
= (f
REF
÷ P) · M ÷ (N
A
· N
B
)
TEST_EN
0
Application mode. Test mode disabled.
Factory test mode is enabled
CLK_STOPx
1
Output Q
x
is disabled in logic low state. Synchronous
disable is only guaranteed if NB = 0.
Output Q
x
is synchronously enabled
MR
The device is reset. The output frequency is zero and
the outputs are asynchronously forced to logic low
state.
After releasing reset (upon the rising edge of MR and
independent on the state of PLOAD), the MPC92433
reads the parallel interface (M, NA, NB and P) to
acquire a valid startup frequency configuration. See
application/programming section.
The PLL attempts to lock to the reference signal.
The t
LOCK
specification applies.
Outputs
LOCK
PLL is not locked
PLL is frequency locked
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參數(shù)描述
MPC92433AE 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
MPC92433AER2 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
MPC92439 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer
MPC92439AC 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
MPC92439ACR2 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
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