Signal Descriptions
ARM DDI 0165B
Copyright 2000 ARM Limited. All rights reserved.
A-9
DBGCOMMRX
Communications
channel receive
Output
When HIGH, this signal denotes that the comms
channel receive buffer contains valid data waiting to
be read by the ARM9E-S.
DBGCOMMTX
Communications
channel transmit
Output
When HIGH, this signal denotes that the comms
channel transmit buffer is empty.
DBGACK
Debug
acknowledge
Output
When HIGH, indicates that the processor is in debug
state.
DBGEN
Debug enable
Input
This input signal allows the debug features of the
processor to be disabled. This signal must be LOW
when debugging is not required.
DBGRQI
Internal debug
request
Output
This signal represents the state of bit 1 of the debug
control register that is combined with EDBGRQ and
presented to the core debug logic.
EDBGRQ
Input
External debug request. An external debugger may
force the processor to enter debug state by asserting
this signal.
DBGEXT[1:0]
EmbeddedICE
external input
Input
This input to the EmbeddedICE logic allows
breakpoints and watchpoints to be dependent on
external conditions.
DBGINSTREXEC
Output
Instruction executed. Indicates that the instruction in
the Execute stage of the processors pipeline has been
executed.
DBGINSTRVALID
Output
Instruction valid. Indicates that the instruction in the
Execute stage of the processors pipeline was valid
and has been executed (unless it failed its conditions
codes).
DBGRNG[1:0]
EmbeddedICE
Rangeout
Output
This output indicates that the corresponding
EmbeddedICE watchpoint unit has matched the
conditions currently present on the address, data and
control buses. This signal is independent of the state
of the enable control bit of the watchpoint unit.
TAPID[31:0]
Boundary scan
ID code
Input
This input specifies the ID code value shifted out on
DBGTDO when the IDCODE instruction is entered
into the TAP controller.
Table A-6 Debug signals (continued)
Name
Direction
Description