
Instruction Cycle Times
8-10
Copyright 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
8.5
Branch and exchange
A Branch and Exchange (BX), Branch, Link and Exchange register (BLX <register>)
or ARM BLX <immediate> operation takes three cycles, and is similar to a Branch:
1.
During the first cycle, the ARM9E-S extracts the branch destination and the new
core state while performing a prefetch from the current PC. This prefetch is
performed in all cases, because by the time the decision to take the branch has
been reached, it is already too late to prevent the prefetch. In the case of BX and
BLX<register>
, the branch destination new state comes from the register. For
BLX<immediate>
the destination is calculated as a PC offset. The state is always
changed. If the previous instruction requested a memory access (and there is no
interlock in the case of BX, BLX <register>), the data is transferred in this
cycle.
2.
During the second cycle, the ARM9E-S performs a fetch from the branch
destination, using the new instruction width, dependent on the state that has been
selected. If the link bit is set, the return address to be stored in r14 is calculated.
3.
During the third cycle, the ARM9E-S performs a fetch from the destination +2 or
+4 dependent on the new specified state, refilling the instruction pipeline.
i
Is the instruction width before the BX/BLX instruction.
i’
Is the instruction width after the BX/BLX instruction.
t’
Is the state of the ITBIT signal after the BX/BLX instruction.
Table 8-6 Branch and exchange cycle timing
Cycle
IA
InMREQ,
ISEQ
INSTR
ITBIT
DA
DnMREQ,
DSEQ
RDATA/
WDATA
1
pc’
N cycle
(pc + 2i)
t’
-
I cycle
2
pc’ + i’
S cycle
(pc’)
t’
-
I cycle
-
3
pc’ + 2i’
S cycle
(pc’ + i’)
t’
-
I cycle
-
(pc’ + 2i’)
-