12-28
MSM66573 Family User's Manual
Chapter 12 Serial Port Functions
[Slave mode]
Figure 12-13 shows the timing diagram of operation during slave mode transmission.
In the slave mode, the transmit clock is input from the transmit clock I/O pin (TXC1). This
external input clock is detected with the edge of CPU clock to generate the transmit shift
clock.
In synchronization with the transmit shift clock that has been generated, the transmission
circuit controls transmission of the transmit data.
The S1BUF write signal (the signal that is output when an instruction to write to S1BUF is
executed, for example "STB A, S1BUF") acts as a trigger to start transmission.
One CPU clock after the write signal is generated, transmit data in S1BUF is set in the
transmit shift register. At this time, synchronized to the signal indicating the beginning of
an instruction (M1S1), a transmit buffer empty signal is generated.
After the transmit data is set (after the fall of the data transfer signal to the transmit shift
register), synchronized to the falling edge of the next transmit shift clock, the transmit data
is output LSB first from the transmit data output pin (TXD1). Thereafter, as specified by
ST1CON and synchronized to the transmit shift clock, transmit data is output to complete
the transmission of one frame.
At this time, if the next transmit data has not been written to S1BUF, a transmit complete
signal is generated in synchronization with M1S1, and the transmission is completed.
TXD1 changes at the falling edge of the transmit shift clock that has been generated from
the detected edge of the externally input TXC1. Therefore, at the receive side, TXD1 is
fetched at the rising edge of TXC1.
Because SIO1 has S1BUF and the transmit shift register which are designed in a duplex
construction, during a transmission it is possible to write the next transmit data to S1BUF.
If S1BUF is written to during a transmission, after the current one frame transmission is
completed, the next transmit data will be automatically set in the transmit shift register, and
the data transmission will continue. After one frame of data is transmitted, if the next data
to be transmitted has been written to S1BUF, the transmit complete signal will not be
generated.
Figure 12-14 shows the timing diagram of operation during continuous transmission.
[Notes]
1. During continuous transmission, there is a time lag of 2 CPU clocks between the current
data transmission and the next data transmission, in which to set the next data. During
this interval, TXD1 is forced to a High level. If an external clock is supplied, insert a
margin of 2 or more CPU clocks between the current data transmission and the next data
transmission.
2. If a transmission error occurs such as causes an external input clock to halt halfway
through the transmission, it is possible to clear the S1BUF data by first setting bit 3
(ST1SLV) of ST1CON to "0" (master mode), then transmitting 8 bits of data. The
ST1CON to "1" after transmitting the 8 bits of data.