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MSM66573 Family User's Manual
Chapter 3 CPU Control Functions
3.3
Reset Function
MSM66573 family is reset by the following four factors.
Low-level input to the
RES input pin
Execution of a break (BRK) instruction
Overflow of the watchdog timer (WDT)
Opcode trap (OPTRP) due to execution of invalid instruction
Resets caused to the above four factors are processed in the same way except that the
address of the vector address to be loaded in the program counter is different.
Table 3-3 lists the vector addresses for each reset factor.
Table 3-3 Vector Address for Each Reset Factor
During the reset processing, arithmetic registers, control registers, mode registers, etc. are
initialized, and the contents of the address pointed to by the vector address is loaded into
the program counter.
For the initial values of different registers, refer to Chapter 20, "Special Function Registers
(SFRs)".
Reset has priority over all other processing (interrupt processing and instruction execution).
Since all processing is aborted, register and RAM contents at that time cannot be
guaranteed.
[Notes]
1. If the
RES pin input is to be used to for reset, apply a low level at the RES pin until the
main clock oscillation stabilizes.
2. Because the internal state and output state at power-on reset are undefined, be sure
to reset the CPU after power is turned on.
3. When applying power to, or disconnecting power from, the VDD and VREF pins, apply
or disconnect the power at the same time for these pins.
The Flash ROM version is reset by the supply voltage sense reset function when the power
supply voltage is dropped, in the same way that the MSM66573 family is reset by low level
input to the
RES input pin. The supply voltage sense reset function is implemented when
the supply voltage for the version operating in the range of 4.5 to 5.5 V is 3.0 V or less and
the supply voltage for the version operating in the range of 2.4 to 3.6 V is 1.5 V or less.
The reset function is not implemented during the STOP mode (only when oscillation clock
is terminated).
Figure 3-5 shows an example of reset pin connection. Table 3-4 lists that status of I/O ports
during reset.
Reset factor
Vector address [H]
Reset caused by low level input to the RES input pin
0000
Reset caused by execution of BRK instruction
0002
Reset caused by overflow of watchdog timer
0004
Reset caused by opcode trap
0006