16-8
MSM66573 Family User's Manual
Chapter 16 Interrupt Processing Functions
Table 16-3 lists the vector address and bit symbol for each maskable interrupt.
If multiple maskable interrupts are generated simultaneously, the lower vector address (in
the order of Table 16-3) is given priority and processed. Similarly, for interrupts that have
been enabled, if the priority level is set and priority control enabled (MIPF = "1"), when
multiple maskable interrupts with the same priority are generated simultaneously, the lower
vector address is given priority and processed.
Table 16-3 Vector Addresses and Bit Symbols for Maskable Interrupts
Interrupt factor
Vector
address [H]
Interrupt
request
Interrupt
enable
Priority level
10
EXINT0 pin input (external interrupt 0)
000A
QINT0
1
No.
Free running counter overflow
000C
QFRCOV
2
CPCM0 event input, compare match
0016
QCPCM0
3
CPCM1 event input, compare match
0018
QCPCM1
4
Timer 0 overflow
001A
QTM0OV
5
EXINT1 pin input (external interrupt 1)
001C
QINT1
6
EXINT2 pin input (external interrupt 2)
001E
QINT2
7
EXINT3 pin input (external interrupt 3)
0020
QINT3
8
Timer 3 overflow
0026
QTM3OV
9
SIO0 transmit buffer empty, transmit
complete, receive complete
0028
QSIO0
10
EXINT4 pin input (external interrupt 4)
002A
QINT4
11
EXINT5 pin input (external interrupt 5)
002C
QINT5
12
Timer 4 overflow
0036
QTM4OV
13
SIO1 transmit buffer empty, transmit
complete, receive complete
0038
QSIO1
14
Timer 5 overflow
003A
QTM5OV
15
SIO3 transmit-receive complete
003E
QSIO3
16
Timer 6 overflow
0042
QTM6OV
17
One cycle of A/D conversion scan channels
complete, A/D conversion select mode complete
0044
QAD
18
Real-time counter output (interval: 0.125 to 1 s)
0048
QRTC
19
PWC0 overflow, match of PWC0 and PWR0
006A
QPWM0
20
PWC1 overflow, match of PWC1 and PWR1
006C
QPWM1
21
Match of PWC0 and PWR2
006E
QPWM2
22
Match of PWC1 and PWR3
0070
QPWM3
23
Timer 9 overflow
0072
QTM9OV
24
P0INT0
P0FRCOV
P0CPCM0
P0CPCM1
P0TM0OV
P0INT1
P0INT2
P0INT3
P0TM3OV
P0SIO0
P0INT4
P0INT5
P0TM4OV
P0SIO1
P0TM5OV
P0SIO3
P0TM6OV
P0AD
P0RTC
P0PWM0
P0PWM1
P0PWM2
P0PWM3
P0TM9OV
EINT0
EFRCOV
ECPCM0
ECPCM1
ETM0OV
EINT1
EINT2
EINT3
ETM3OV
ESIO0
EINT4
EINT5
ETM4OV
ESIO1
ETM5OV
ESIO3
ETM6OV
EAD
ERTC
EPWM0
EPWM1
EPWM2
EPWM3
ETM9OV
P1INT0
P1FRCOV
P1CPCM0
P1CPCM1
P1TM0OV
P1INT1
P1INT2
P1INT3
P1TM3OV
P1SIO0
P1INT4
P1INT5
P1TM4OV
P1SIO1
P1TM5OV
P1SIO3
P1TM6OV
P1AD
P1RTC
P1PWM0
P1PWM1
P1PWM2
P1PWM3
P1TM9OV