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MSM66573 Family User's Manual
Chapter 16 Interrupt Processing Functions
16.3.3 Priority Control of Maskable Interrupts
Three levels of priority can be set for each maskable interrupt factor, resulting in easy to
realize control of multiple interrupts. Priority control in actual programs is described below.
(1)
Basic interrupt control
When a maskable interrupt occurs, since the reception of other maskable interrupts is
automatically disabled (MIE = "0"), other interrupts (except for nonmaskable interrupts and
reset processing) will not occur within the interrupt processing routine. If another maskable
interrupt is generated during execution of the interrupt routine, that interrupt will wait for
processing. In such a case, immediately after processing of the first interrupt is completed,
processing of the interrupt that has been waiting will begin. (See Figure 16-3.) If several
interrupts are awaiting processing, the interrupt vector with the lowest address will be
processed first. (See Table 16-3.)
(2)
Multiple interrupt control
During execution of an interrupt routine, other maskable interrupts may be enabled. This
is known as "multiple interrupt control". If multiple interrupt control is required, make a
setting so that multiple interrupts will be enabled (MIE = "1") within the maskable interrupt
routine when a maskable interrupt occurs.
The following two methods exist for multiple interrupt control.
(i) Control by IE flags
(ii) Control by MIPF (Master Interrupt Priority Flag)
(i) Control by IE flags
In the interrupt processing routine, only those IE flags that correspond to the multiple
interrupt factors to be enabled are set to "1". Multiple interrupts from other factors are
disabled by setting their IE flags to "0".
Next, by setting the MIE flag to "1" within the interrupt processing routine, the reception of
multiple interrupts for the enabled interrupt factors enabled by setting the IE flags to "1" will
begin. (See Figure 16-4.)
If an interrupt occurs for which the corresponding IE flag is "0" while another interrupt is
being processed, the interrupt will wait until the interrupt process being executed is
completed and the program changes its IE flag to "1".
(ii) Control by MIPF (Master Interrupt Priority Flag)
In addition to the control of (i) above, by setting MIPF to "1", the priority of maskable
interrupts can be controlled by the hardware. Of the enabled interrupt factors specified with
IE = "1", multiple interrupts are enabled only for those interrupt factors whose priority is
higher than that of the interrupt currently being processed. (If MIPF = "0", then all interrupt
factors with IE specified as "1" will be enabled for multiple interrupts.)
If interrupts are generated having the same or lower priority than that of the interrupt process
currently being executed, those interrupts will wait until completion of the interrupt process
currently being executed. After completion of the interrupt process, if several interrupts are
waiting, they will be executed in order of highest priority. However, if there are several
interrupts with the same priority level, the interrupt with the lowest vector address will be
processed first. (See Table 16-3.)