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MSM66573 Family User's Manual
Chapter 2 CPU Architecture
2
2.3.5 Segment Registers
There are three 8-bit segment registers: the code segment register (CSR), the table
segment register (TSR) and the data segment register (DSR). These registers select
segments in the program memory space.
However, since the program memory space has only segments 0 to 15, only bits 0 to 3 are
valid. Bits 4 to 7 are fixed to "0".
(1)
Code segment register (CSR)
CSR specifies the segment in program memory space to which the program code currently
being executed belongs. CSR exists as an independent 8-bit register and is not assigned
to the SFR area. The CSR contents can be overwritten by FJ, FCAL, VCAL, FRT and RTI
instructions and interrupts. No other methods can be used to overwrite the contents of CSR.
FJ and FCAL instructions, use branch destination addresses that are within segments 0 to
15.
Each segment is assigned an internal segment offset address of 0 to 0FFFFH. The address
calculation to determine the addressed target is performed with a 16-bit offset address and
any resulting overflow or underflow is ignored so that CSR is does not change. Similarly,
overflow of the PC never updates the CSR. Therefore, without the use of the CSR overwrite
method described above, program execution does not advance beyond the code segment
boundary. The CSR value at reset is 00H.
When an interrupt occurs after program memory space has been expanded to 1MB, both
the current CSR value and the PC are automatically saved on the stack. Executing a RTI
instruction restores the saved value to CSR. (Refer to Section 2.2.1, "Memory Space
Expansion".)
(2)
Table segment register (TSR)
TSR specifies the segment in program memory to which the table data belongs. TSR is an
8-bit register and is assigned to the SFR area. The contents of TSR can be overwritten by
instructions that use SFR addressing. Data in the table segment can be accessed by using
ROM reference instructions (LC, LCB, CMPC and CMPCB). If the ROM window function
is used, RAM addressing can be utilized for this table segment. Only bits 0 to 3 of TSR are
valid. If read, a value of "0" will be obtained for bits 4 to 7. If writing to TSR, "0" must be
written to bits 4 to 7.
"0"
76543210
CSR
At reset
00000000
"0"
76543210
TSR
At reset
00000000
"0" indicates that a value of "0" must be written.
If read, a value of "0" will be obtained.
Address: 0008 [H]
R/W access: R/W