參數(shù)資料
型號: MSM80C86A-10RS
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 10 MHz, MICROPROCESSOR, PDIP40
封裝: 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40
文件頁數(shù): 10/38頁
文件大?。?/td> 298K
代理商: MSM80C86A-10RS
17/37
Semiconductor
MSM80C86A-10RS/GS/JS
RQ/GT0
RQ/GT1
REQUEST/GRANT:Input/Output
These lines are used for Bus Request from other devices and Bus GRANT to other devices.
These lines are bidirectional and active low.
LOCK
LOCK:Output
This line is active low.
When this line is low, other devices cannot gain control of the bus.
This line is high impedance during hold acknowledge.
QS0/QS1
QUEUE STATUS: Output
These lines are Queue Status, and indicate internal instruction queue status.
0
Read I/O Port
0 (LOW)
Interrupt acknowledge
S2
0
1
0
S1
Characteristics
Write I/O Port
Halt
1
0
1
0
1
Read Memory
1 (HIGH)
Code Access
0
1
0
Write Memory
Passive
1
0
1
0
S0
The following pin function descriptions are minimum mode only. Other pin functions are
already described.
M/IO
STATUS: Output
This line selects memory address space or I/O address space.
When this line is high, the CPU selects memory address space and when it is low, the CPU
selects I/O address space.
This line is high impedance during hold acknowledge.
WR
WRITE: Output
This line indicates that the CPU is in the memory or I/O write cycle.
This line is a write strobe signal when the CPU writes data to memory of I/O device.
This line is active low.
This line is high impedance during hold acknowledge.
0
1 (HIGH)
1
First Byte of Op Code from Queue
0 (LOW)
No operation
QS1
1
0
1
0
QS0
Characteristics
Empty the Queue
Subsequent Byte from Queue
相關(guān)PDF資料
PDF描述
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