參數(shù)資料
型號: MSM80C86A-10RS
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 10 MHz, MICROPROCESSOR, PDIP40
封裝: 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40
文件頁數(shù): 7/38頁
文件大小: 298K
代理商: MSM80C86A-10RS
14/37
Semiconductor
MSM80C86A-10RS/GS/JS
Asynchronous Signal Recognition
CLK
Signal
NMI
INTR
TEST
tINVCH (See NOTE 1)
NOTE: 1 Setup requirements for asynchronous
signals only to guarantee recognition
at next CLK
Hold/Hold Acknowledge Timing (Minimum Mode Only)
Request/Grant Sequence Timing (Maximum Mode Only)
Bus Lock Signal Timing (Maximum Mode Only)
Reset Timing
CLK
LOCK
tCLAV
Any CLK Cycle
tCLAV
CLK
HOLD
AD15 - AD0,
A19/S6 - A16/S3,
RD,
BHE/S7, M/IO
DT/R, WR, DEN
HLDA
MSM80C86A-10
Coprocessor
MSM80C86A-10
≥ 1 CLK Cycle
1 or 2 Cycles
tHVCH
tCLHAV
tCLAZ
≥ 50msec
tDVCL
CLK
tCLDX
Reset
VCC
≥ 4 CLK Cycles
Any CLK Cycle
CLK
RQ/GT
AD15 - AD0
A19/S6 - A16/S3
S2, S1, S0,
RD, CLOCK
BHE/S7
tCLGH
≥ tCLCL
tGVCH
tCHGX
tCLGL
≥ tCLCL
tCLGH
tCLAZ
Pulse 3
Coprocessor
Release
MSM80C86A-10
Coprocessor
MSM80C86A-10
(See NOTE 1)
NOTE: 1 The coprocessor may not drive the buses outside the region shown without risking contention.
Pulse 1
Coprocessor
RQ
Pulse 2
80C86AGT
> 0 CLK Cycle
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