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參數(shù)資料
| 型號(hào)： | MSM80C86A-10RS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 10 MHz, MICROPROCESSOR, PDIP40 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 15/38頁 |
| 文件大?。?/td> | 298K |
| 代理商： | MSM80C86A-10RS |
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Semiconductor
MSM80C86A-10RS/GS/JS
Minimum and Maximum Modes
The MSM80C86A-10 has two system modes: minimum and maximum. When using maximum
mode, it is easy to organize a multi-CPU system with a MSM82C88-2 Bus Controller which
generates the bus control signal.
When using minimum mode, it is easy to organize a simple system by generating bus control
signal by itself.
MN/MX is the mode select pin. Definition of 24-31 pin changes depend on the MN/MX pin.
Bus Operation
The MSM80C86A-10 has a time multiplexed address and data bus. If a non-multiplexed bus is
desired for a system, it is only to add the address latch.
A CPU bus cycle consists of at least four clock cycles: T1, T2, T3 and T4. (Fig. 4)
The address output occurs during T1 and data transfer occurs during T3 and T4. T2 is used for
changing the direction of the bus at the read operation. When the device which is accessed by
the CPU is not ready for The data transfer and the CPU “NOT READY”, TW cycles are inserted
between T3 and T4.
When a bus cycle is not needed, T1 cycles are inserted between the bus cycles for internal
execution. During the T1 cycle, the ALE signal is output from the CPU or the MSM82C88-2
depending on MN/MX. At the trailing edge of ALE, a valid address may be latched.
Status bits S0, S1 and S2 are used in the maximum mode by the bus controller to recognize the
type of bus operation according to the following table.
Status bits S3 through S7 are multiplexed with A16 - A19, and BHE: therefore, they are valid
during T2 through T4.
S3 and S4 indicate which segment register was selected on the bus cycle, according to the
following table.
0
Read I/O
0 (LOW)
Interrupt acknowledge
S2
0
1
0
S1
Characteristics
Write I/O
Halt
1
0
1
0
1
Read Data from Memory
1 (HIGH)
Instruciton Fetch
0
1
0
Write Data to Memory
Passive (no bus cycle)
1
0
1
0
S0
0
1 (HIGH)
1
Stack
0 (LOW)
Alternate Data (Extra segment)
S4
1
0
1
0
S3
Characteristics
Code or None
Data
I/O Addressing
The MSM80C86A-10 has 64 Kbytes of I/O or as 32 Kwords I/O. When the CPU accesses an I/
O device, addresses AD0 - AD15 are in the same format as a memory address, and A16 - A19 are
low.
The I/O ports addresses are same as memory, so it is necessary to be careful when using 8-bit
peripherals.
S5 indicates interrupt enable Flag.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM80C88A-10GS | 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56 |
| MSM80C88A-10RS | 8-BIT, 10 MHz, MICROPROCESSOR, PDIP40 |
| MSM80C88A-10JS | 8-BIT, 10 MHz, MICROPROCESSOR, PQCC44 |
| MSM80C88A-10GS-K | 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56 |
| MSM81C55-5GS-2K | 22 I/O, PIA-GENERAL PURPOSE, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM80C88A-10GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR |
| MSM80C88A-10JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR |
| MSM80C88A-10RS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR |
| MSM80C88A2JS | 制造商:OKI 功能描述:* |
| MSM8128 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
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