參數(shù)資料
型號(hào)： MSM80C86A-10RS
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 10 MHz, MICROPROCESSOR, PDIP40
封裝： 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40
文件頁(yè)數(shù)： 13/38頁(yè)
文件大?。?/td> 298K
代理商： MSM80C86A-10RS
19/37
Semiconductor
MSM80C86A-10RS/GS/JS
FUNCTIONAL DESCRIPTION STATIC OPERATION
The MSM80C86A-10 circuitry is of static design. Internal registers, counters and latches are
static and require no refresh as with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other microprocessors. The MSM80C86A-10 can
operate from DC to the appropriate upper frequency limit. The processor clock may be stopped
in either state (high/low) and held there indefinitely. This type of operation is especially useful
for system debug or power critical applications.
The MSM80C86A-10 can be single stepped using only the CPU clock. This state can be
maintained as long as is necessary. Single step clock operation allows simple interface circuitry
to provide critical information for bringing up your system.
Static design also allows very low frequency operation (down to DC). In a power critical
situation, this can provide extremely low power operation since MSM80C86A-10 power
dissipation is directly related to operating frequency. As the system frequency is reduced, so
is the operating power until, ultimately, at a DC input frequency, MSM80C86A-10 power
requirement is the standby current (500mA maximum).
General Operation
The internal function of the MSM80C86A-10 consists of a Bus Interface Unit (BIU) and an
Execution Unit (EU). These units operate mutually but perform as separate processors.
BIU performs instruction fetch and queueing, operand fetch, DATA read and write address
relocation and basic bus control. Instruction pre-fetch is performed while waiting for decording
and execution of instructions. Thus, the CPU’s performance is increased. Up to 6-bytes of
instructions stream can be queued.
The EU receives pre-fetched instructions from the BIU queue, decodes and executes the
instructions, and provides the un-relocated operand address to BIU.
Memory Organization
The MSM80C86A-10 has a 20-bit address to memory. Each address has an 8-bit data width.
Memory is organized 00000H to FFFFFH and is logically divided into four segments: code, data,
extra data and stack segment. Each segment contains up to 64 Kbytes and locates on a 16-byte
boundary. (Fig. 3a)
All memory references are made relative to the segment register which functions in accordance
with a select rule. Word operands can be located on even or odd address boundary.
The BIU automatically performs the proper number of memory accesses. Memory consists of
an even address and an odd address. Byte data of even address is transferred on the AD0-AD7
and byte data of odd address is transfered on the AD8-AD15.
The CPU provides two enable signals BHE and A0 to access either an odd address, even address
or both:
Memory location FFFF0H is the start address after reset, and 00000H through 003FFH are
reserved as an interrupt pointer, where there are 256 types of interrupt pointers.
Each interrupt type has a 4-byte pointer element consisting of a 16-bit segment address and a
16-bit offset address.
相關(guān)PDF資料
PDF描述
MSM80C88A-10GS 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56
MSM80C88A-10RS 8-BIT, 10 MHz, MICROPROCESSOR, PDIP40
MSM80C88A-10JS 8-BIT, 10 MHz, MICROPROCESSOR, PQCC44
MSM80C88A-10GS-K 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56
MSM81C55-5GS-2K 22 I/O, PIA-GENERAL PURPOSE, PQFP44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM80C88A-10GS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR
MSM80C88A-10JS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR
MSM80C88A-10RS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR
MSM80C88A2JS 制造商:OKI 功能描述:*
MSM8128 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM
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