參數(shù)資料
型號： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 1/94頁
文件大小： 4179K
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb: x4, x8, x16 DDR SDRAM
Features
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_1.fm - Rev. J 1/06 EN
1
2000–2005 Micron Technology, Inc. All rights reserved.
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
Features
VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data (x16 has two
– one per byte)
Programmable burst lengths: 2, 4, or 8
Auto refresh and self refresh modes
Longer lead TSOP for improved reliability (OCPL)
2.5V I/O (SSTL_2 compatible)
Concurrent auto precharge option is supported
tRAS lockout supported (tRAP = tRCD)
Options
Marking
Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
128M4
64 Meg x 8 (16 Meg x 8 x 4 banks)
64M8
32 Meg x 16 (8 Meg x 16 x 4 banks)
32M16
Plastic Package
66-pin TSOP
TG
66-pin TSOP Lead-free
P
60-Ball FBGA (10 x 12.5mm)
FN
60-Ball FBGA (10 x 12.5mm) Lead-free
BN
Timing – cycle time
5ns @ CL = 3 (DDR400B)
-5B
6ns @ CL = 2.5 (DDR333) (FBGA only)
-6
6ns @ CL = 2.5 (DDR333) (TSOP only)
-6T
7.5ns @ CL = 2 (DDR266)
-75E
7.5ns @ CL = 2 (DDR266A)
-75Z
7.5ns @ CL = 2.5 (DDR266B)
-75
Self refresh
Standard
None
Low-Power self refresh
L
Temperature rating
Standard (0°C to +70°C)
None
Industrial (-40°C to +85°C)
IT
Revision
x4, x8, x16
:C
x4, x8
:D
x4, x8, x16
:F
Table 1:
Addressing Configuration
128 Meg x 4
64 Meg x 8
32 Meg x 16
Configuration
32 Meg x 4 x 4 banks
16 Meg x 8 x 4 banks
8 Meg x 16 x 4 banks
Refresh count
8K
Row addressing
8K (A0–A12)
Bank addressing
4 (BA0, BA1)
Column addressing
4K (A0-A9, A11, A12)
2K (A0–A9, A11)
1K (A0–A9)
Table 2:
Key Timing Parameters
CL = CAS (Read) latency; data-out window is MIN clock rate with 50% duty cycle @ CL = 2, CL = 2.5, or CL = 3
Speed
Grade
Clock Rate
Data-Out Window
Access
Window
DQS–DQ
Skew
CL = 2
CL = 2.5
CL = 3
-5B
133 MHz
167 MHz
200 MHz
1.6ns
±0.70ns
+0.40ns
-6
133 MHz
167 MHz
NA
2.1ns
±0.70ns
+0.40ns
6T
133 MHz
167 MHz
NA
2.0ns
±0.70ns
+0.45ns
-75E/-75Z
133 MHz
NA
2.5ns
±0.75ns
+0.50ns
-75
100 MHz
133 MHz
NA
2.5ns
±0.75ns
+0.50ns
相關(guān)PDF資料
PDF描述
MT46V128M4P-75L:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V128M4P-75ZLIT:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4TG-75E 64M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4FG-75Z 64M X 4 DDR DRAM, 0.75 ns, PBGA60
MT47H128M8HQ-3AT 128M X 8 DDR DRAM, 0.4 ns, PBGA60
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