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參數資料
| 型號： | MT46V128M4FN-75E:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 10 X 12.50 MM, FBGA-60 |
| 文件頁數： | 17/94頁 |
| 文件大?。?/td> | 4179K |
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09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
24
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Commands
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the
rest of the system is powered down. When in the self refresh mode, the DDR SDRAM
retains data without external clocking. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically dis-
abled upon entering SELF REFRESH and is automatically enabled upon exiting SELF
REFRESH (A DLL reset and 200 clock cycles must then occur before a READ command
can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH. VREF
voltage is also required for the full duration of SELF REFRESH.
The procedure for exiting self refresh requires a sequence of commands. First, CK and
CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM
must have NOP commands issued for tXSNR because time is required for the comple-
tion of any internal refresh in progress. A simple algorithm for meeting both refresh and
DLL requirements is to apply NOPs for tXSNR time, then a DLL RESET (via the extended
mode register) and NOPs for 200 additional clock cycles before applying any other com-
mand.
相關PDF資料 |
PDF描述 |
|---|---|
| MT46V128M4P-75L:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V128M4P-75ZLIT:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4TG-75E | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
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參數描述 |
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