參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁(yè)數(shù)： 11/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
19
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Extended Mode Register
Operating Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command
with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required
by the Micron device, JEDEC specifications recommend that a LOAD MODE REGISTER
command resetting the DLL should always be followed by a LOAD MODE REGISTER
command selecting normal operating mode.
All other combinations of values for A7–A12 are reserved for future use and/or test
modes. Test modes and reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, and output drive strength.
These functions are controlled via the bits shown in Figure 9 on page 20. The extended
mode register is programmed via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is pro-
grammed again or the device loses power. The enabling of the DLL should always be fol-
lowed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both
LOW) to reset the DLL.
The extended mode register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time before initiating any subse-
quent operation. Violating either requirement could result in unspecified operation.
Output Drive Strength
The normal drive strength for all outputs are specified to be SSTL2, Class II. The x16 sup-
ports a programmable option for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The selection of the reduced
drive strength will alter the DQ pins and DQS pins from SSTL2, Class II drive strength to
a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive
strength.
DLL Enable/Disable
When the part is running without the DLL enabled, device functionality may be altered.
The DLL must be enabled for normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE
HIGH must occur before a READ command can be issued.
Table 5:
CAS Latency (CL)
Speed
Allowable Operating Clock Frequency (MHz)
CL = 2
CL = 2.5
CL = 3
-5B
75
≤ f ≤ 133
75
≤ f ≤ 167
133
≤ f ≤ 200
-6/-6T
75
≤ f ≤ 133
75
≤ f ≤ 167
–
-75E
75
≤ f ≤ 133
75
≤ f ≤ 133
–
-75Z
75
≤ f ≤ 133
75
≤ f ≤ 133
–
-75
75
≤ f ≤ 100
75
≤ f ≤ 133
–
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