參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 9/94頁
文件大小： 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
17
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Register Definition
Notes:
1. Whenever a boundary of the block is reached within a given sequence above, the fol-
lowing access wraps within the block.
2. For BL = 2, A1–Ai select the two-data-element block; A0 selects the first access within
the block.
3. For BL = 4, A2–Ai select the four-data-element block; A0–A1 select the first access
within the block.
4. For BL = 8, A3–Ai select the eight-data-element block; A0–A2 select the first access
within the block.
Table 4:
Burst Definition
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type= Sequential
Type= Interleaved
2
A0
00-1
0-1
11-0
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
相關(guān)PDF資料
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MT46V128M4P-75L:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
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