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| 型號(hào)： | MT46V32M81AZ4-6T:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁(yè)數(shù)： | 21/82頁(yè) |
| 文件大小： | 2866K |
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128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
28
2000 Micron Technology, Inc. All rights reserved.
Figure 19: READ to PRECHARGE
NOTE:
1. DO n = data-out from column n.
2. Burst length = 4, or an interrupted burst of 8.
3. Three subsequent elements of data-out appear in the programmed order following DO n..
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
5. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also assumed that tRAS (MIN) is
met.
6. A READ command with AUTO-PRECHARGE enabled, provided tRAS(MIN) is met, would cause a precharge to be per-
formed at x number of clock cycles after the READ command, where x = BL / 2.
7. An active command to the same bank is only allowed if tRC (MIN) has been satisfied.
8. PRE = PRECHARGE command; ACT = ACTIVE command.
CK
CK#
COMMAND6
READ
NOP
PRE
NOP
ACT7
ADDRESS
Bank a,
Col n
Bank a,
(a or all)
Bank a,
Row
READ
NOP
PRE
NOP
ACT7
Bank a,
Col n
CL = 2
tRP
CK
CK#
COMMAND6
ADDRESS
DQ
DQS
CL = 2.5
DQ
DQS
DO
n
DO
n
T0
T1
T2
T3
T2n
T3n
T4
T5
T0
T1
T2
T3
T2n
T3n
T4
T5
Bank a,
(a or all)
Bank a,
Row
DON’T CARE
TRANSITIONING DATA
READ
NOP
PRE
NOP
ACT7
Bank a,
Col n
tRP
CK
CK#
COMMAND6
ADDRESS
DQ
DQS
CL = 3
DO
n
T0
T1
T2
T3
T4n
T3n
T4
T5
Bank a,
(a or all)
Bank a,
Row
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相關(guān)代理商/技術(shù)參數(shù) |
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