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參數(shù)資料
| 型號： | MT46V32M81AZ4-6T:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 6/82頁 |
| 文件大?。?/td> | 2866K |
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128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
14
2000 Micron Technology, Inc. All rights reserved.
NOTE:
1. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
2. For a burst length of two, A1-Ai select the two-
data-element block; A0 selects the first access
within the block.
3. For a burst length of four, A2-Ai select the four-
data-element block; A0-A1 select the first access
within the block.
4. For a burst length of eight, A3-Ai select the eight-
data-element block; A0-A2 select the first access
within the block.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, 2.5, or 3 (DDR400 only) clocks, as
shown in Figure 8.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 5,
CAS Latency (CL), on page 14 indicates the operating
frequencies at which each CAS latency setting can be
used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
Figure 8: CAS Latency
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7-A11
each set to zero, and bits A0-A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9-A11 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
Table 4:
Burst Definition
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN A
BURST
TYPE=
SEQUENTIAL
TYPE=
INTERLEAVED
2
A0
00-1
0-1
11-0
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Table 5:
CAS Latency (CL)
SPEED
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
CL = 2
CL = 2.5
CL = 3
-5B
75
≤ f ≤ 133
75
≤ f ≤ 167
133
≤ f ≤ 200
-6/-6T
75
≤ f ≤ 133
75
≤ f ≤ 167
–
-75E
75
≤ f ≤ 133
75
≤ f ≤ 133
–
-75Z
75
≤ f ≤ 133
75
≤ f ≤ 133
–
-75
75
≤ f ≤ 100
75
≤ f ≤ 133
–
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
READ
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON’T CARE
TRANSITIONING DATA
CK
CK#
COMMAND
DQ
DQS
CL = 3
READ
NOP
T0
T1
T2
T3
T3n
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