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參數(shù)資料
| 型號(hào)： | MT46V32M81AZ4-6T:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 58/82頁 |
| 文件大?。?/td> | 2866K |
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128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
61
2000 Micron Technology, Inc. All rights reserved.
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs (except for IDD measurements) measured
with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC)
and VIH(AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the
DC value. Thus, from VDDQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. VID is the magnitude of the difference between
the input level on CK and the input level on CK#.
9. The value of VIX and VMP are expected to equal
VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
10. IDD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle times at CL = 3 for -5B, CL = 2.5 for -6/-
6T and -75, and CL=2 for -75E/-75Z speeds with
the outputs open.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
13. This parameter is sampled. VDD=+2.5V±0.2V,
VDDQ=+2.5V±0.2V, VREF=VSS, f=100MHz, TA=25°C
VOUT(DC)=VDDQ/2, VOUT (peak to peak)=0.2V.
DM input is grouped with I/O pins, reflecting the
fact that they are matched in loading.
14. For slew rates less than 1V/ns and greater than or
equal to 0.5Vns. If slew rate is less than 0.5V/ns,
timing must be derated: tIS has an additional 50ps
per each 100mV/ns reduction in slew rate from
500mV/ns, while tIH has 0pF is unaffected. If slew
rate exceeds 4.5V/ns, functionality is uncertain.
For -5B, -6, and -6T speed grades, slew rates must
be greater than or equal 0.5V/ns.
15. The CK/CK# input reference level (for timing ref-
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is VREF.
16. Inputs are not recognized as valid until VREF stabi-
lizes. Once initialized, including self refresh mode,
VREF must be powered within specified range.
Exception: during the period before VREF stabi-
lizes, CKE 0.3 x VDDQ is recognized as LOW.
17. The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
VTT.
18. Transitions occur in the same access time win-
dows as data valid transitions. These parameters
are not referenced to a specific voltage level, but
specify when the device output is no longer driv-
ing (tHZ) or begins driving (tLZ).
19. The intent of the Don’t Care state after completion
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high (above VIHDC(MIN) then it must
not transition low (below VIHDC) prior to
tDQSH(MIN).
20. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
Output
(VOUT)
Reference
Point
50
VTT
30pF
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