參數(shù)資料
型號： MT58L512L18PS-7.5IT
元件分類： SRAM
英文描述： 512K X 18 CACHE SRAM, 4 ns, PQFP100
封裝： PLASTIC, MS-026BHA, TQFP-100
文件頁數(shù)： 23/32頁
文件大?。?/td> 616K
代理商： MT58L512L18PS-7.5IT
3
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18P_2.p65 – Rev. 6/01
2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION
The Micron SyncBurst SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x
18, 256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#). Note that CE2# is not available on the
T Version.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQa’s and DQPa; BWb# con-
trols DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. GW# LOW causes all
bytes to be written. Parity bits are only available on the
x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state tKQHZ nanoseconds after the rising edge
of clock.
Micron’s 8Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for Pentium
and PowerPC pipelined systems and systems that ben-
efit from a very wide, high-speed data bus. The device
is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
TQFP PINOUTS
At the time of the writing of this data sheet, there are
two pinouts in the industry. Micron will support both
pinouts for this part.
相關(guān)PDF資料
PDF描述
MT78740 RELAY SOCKET
MT78745 RELAY SOCKET
MT9KDF12872PZ-1G6XX 128M X 72 DDR DRAM MODULE, DMA240
MTE-28-T INTERCONNECTION DEVICE
MTE-11-T INTERCONNECTION DEVICE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT58L512L18PT-10 制造商:Cypress Semiconductor 功能描述:512KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT58L512L18PT-7.5 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT58L512L18PT-7.5 IT 制造商:Cypress Semiconductor 功能描述:512KX18 SRAM PLASTIC IND TEMP
MT58L512V18F 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L512V18P 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 PIPELINED, SCD SYNCBURST SRAM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*