參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 135/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
9
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
SIGNAL DESCRIPTIONS
This section describes each signal used by the Cop-
perhead chipset.
Signals which are active LOW are denoted with a “#”
suffix.
Buses are denoted with the bit range enclosed by
brackets “[]”
The least significant bit on a bus is the lower
number.
Shared signals are denoted with a “/”
the primary signal name is on the left side of “/”
the secondary signal name is on the right side of “/”
The following notations are used to describe the sig-
nal type:
IInput Pin
OOutput Pin
OD Open Drain
I/O Bidirectional Input/Output Pin
Host Interface Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
A20GATE
I
VDD3.3
A20 Gate. This signal is from the keyboard controller. It acts as an alterna-
tive method to force the H_A20M# signal active. Internally this signal is
OR’d with the Port 92h Fast A20 and the USB A20 to produce A20M# to the
processor.
H_A20M#
OD
VDD2.5
Mask A20. H_A20M# will go active based on either setting the appropriate
bit in the Port 92h register, the USB A20 is active under legacy USB key-
board/mouse emulation, or based on the A20GATE input being active.
H_FERR#
I
VDD2.5
Numeric Coprocessor Error. This signal is tied to the coprocessor error sig-
nal on the CPU. H_FERR# is only used if the I/O Controller coprocessor error
reporting function is enabled in the General Control Register (Function 0,
Offset 40h, bit 14). If H_FERR# is asserted, the I/O Controller generates an
internal IRQ 13 to its interrupt controller unit. It is also used to gate the
H_IGNNE# signal to ensure that H_IGNNE# is not asserted to the processor
unless H_FERR# is active. H_FERR# requires an external weak pull-up to
ensure a high level when the coprocessor error function is disabled.
H_IGNNE#
OD
VDD3.3
Ignore Numeric Error. H_IGNNE# is only used if the I/O Controller coproces-
sor error reporting function is enabled in the General Control Register
(Function 0, Offset 40h, bit 14). If H_FERR# is active, indicating a coproces-
sor error, a write to the Coprocessor Error Register (F0h) causes the
H_IGNNE# to be asserted. H_IGNNE# remains asserted until H_FERR# is
negated. If H_FERR# is not asserted when the Coprocessor Error Register is
written, the H_IGNNE# signal is not asserted. H_IGNNE# requires an exter-
nal weak pull-up to ensure a high level to the processor.
H_INIT#
OD
VDD2.5
Initialization. H_INIT# is asserted by the I/O Controller for 16 PCI clocks to
reset the processor. H_INIT# requires an external weak pull-up to ensure a
high level to the processor.
H_INTR
OD
VDD2.5
Processor Interrupt. H_INTR is asserted by the I/O Controller to signal the
processor that an interrupt request is pending and needs service. It is an
asynchronous output and normally driven low. H_INTR requires an external
weak pull-up to ensure a high level to the processor.
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