參數(shù)資料
型號: MT8LLN22NCNE
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA316
封裝: 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù): 96/145頁
文件大?。?/td> 2285K
代理商: MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
54
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Subsystem ID (Device 7h, Function 2h)
NOTE: 1. The sub-system write protection bit (bit 0 of register 68h) controls The read/write attribute.
Capabilities Pointer (Device 7h, Function 2h)
NOTE: 1. The Capabilities List enabled attribute is controlled by the capability disable bit (bit 1 of register 68h). When this
bit is set the Capabilities list is disabled this field will return all zeros.
Interrupt Line (Device 7h, Function 2h)
Interrupt Pin (Device 7h, Function 2h)
ADDRESS: 2Eh-2Fh
SYMBOL: SID
BITS
DESCRIPTION
PROPERTIES
RESET
NOTES
31:16
Subsystem ID.
R/WP
0000h
1
ADDRESS: 34h-37h
SYMBOL: CAP_PTR
BITS
DESCRIPTION
PROPERTIES
RESET
NOTES
31:8
Reserved.
R/O
000000h
7:0
Capabilities List Pointer.
R/O
60h
1
ADDRESS: 3Ch
SYMBOL: INT_LINE
BITS
DESCRIPTION
PROPERTIES
RESET
7:0
Interrupt Line.
R/W
00h
ADDRESS: 3Dh
SYMBOL: INT_PIN
BITS
DESCRIPTION
PROPERTIES
RESET
7:0
Interrupt Pin.
R/O
01h
IDE Primary Drive 0 Timing and Control (Device 7h, Function 2h)
ADDRESS: 40h-43h
SYMBOL: TIM_CTRL_P0
BITS
DESCRIPTION
PROPERTIES
RESET
31:26
Throttle/tDVS
Relaxation time between IORD or IOWR Command pulses. In Sync DMA
Mode, this field is programmed to the required data setup time (tDVS).
R/W
17h
25:20
Command/tCYC
IORD and IOWR pulse width time. In Sync DMA mode, this is pro-
grammed to the STROBE cycle time (tCYC).
R/W
15h
19:17
Set-up tACK/tENV
This field is programmed to the PIO set-up time or the tACK/tENV time
required for all Sync DMA modes.
R/W
110b
16:13
Ready Pause Time (Sync DMA Mode Only)
This field is programmed to the Interlock time (tRP) as specified for Sync
DMA.
R/W
0
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