參數(shù)資料
型號(hào)： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 78/145頁
文件大小： 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
38
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Extended I/O APIC Control (Device 7h, Function 0h)
ADDRESS: A1h
SYMBOL: IOAPIC
BITS
DESCRIPTION
PROPERTIES
RESET
7
Enable expanded PCI Interrupt (P_INT[15:0]) routing to 8259’s. When set,
P_INT[15:0] will be routed to the 8259’s based on their corresponding
interrupt routing register. When clear, P_INT[15:0] will be routed to the
8259’s based on P_INT[D:A] routing.
R/W
0
6
Retry acceptance exception. When set, retry for Status A1 will cause the
Arbitration ID to increment
R/W
0
5
Status A1 increment exception. When set, Status A1 will cause the arbiter
to increment to the next interrupt to be delivered.
R/W
0
4
Lowest priority zeros accepted. When set a Status A1 of zeros will be
used as an acceptance for lowest priority interrupts.
R/W
0
3
Deassert message enable. When set, deassert messages will be transmit-
ted on the APIC bus.
R/W
0
2
PCI Message signaled interrupt EOI support enable. When set writes to
the IRQ pin assertion register will cause interrupt delivery status to be
set.
R/W
0
1
PCI Message signaled interrupt request support enable. When set writes
to the EOI assertion register will cause Remote IRR status to clear.
R/W
0
Expanded I/O APIC Disable. When set, the I/O supports the standard 24
interrupt inputs. When clear, the I/O APIC supports the expanded 40
interrupt inputs.
P_INT[15:0] are connected internally to P_INT[D:A] as follows:
P_INT[0,4,8,12] to P_INT[A].
P_INT[1,5,9,13] to P_INT[B].
P_INT[2,6,10,14] to P_INT[C].
P_INT[3,7,11,15] to P_INT[D].
R/W
0
Extended Trap Control (Device 7h, Function 0h)
ADDRESS: A2h
SYMBOL: EXT_TRAP
BITS
DESCRIPTION
PROPERTIES
RESET
7:4
Reserved
R/W
0
3
GPA1R. Capture writes enable. When set, the south bridge will observe
the address, data, byte enables, and command for a write transaction
that falls into the General Purpose Trap Address 1 (GPTA1) and store
them in TRAP_ADDR, TRAP_DATA, and TRAP_CMND. The address, status,
and space type is defined in GPAR1. The address bits to be masked as
part of the trap are defined in DEVCTL. The trap will be performed inde-
pendent of whether SMI traps are enabled in general or if the SMI trap is
enabled for GPTA1.
R/W
0
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